# Reading C:/modeltech_10.0c/tcl/vsim/pref.tcl 
# //  ModelSim SE 10.0c Jul 21 2011 
# //
# //  Copyright 1991-2011 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# OpenFile D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/tb_ram_fir.mpf 
# Loading project tb_ram_fir
#  
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v failed with 2 errors.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 2 failed with 3 errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v failed with 2 errors.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 1 failed with 2 errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v failed with 1 errors.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v failed with 2 errors.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 1 failed with 2 errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v failed with 1 errors.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
 vsim -novopt +nowarnTSCALE work.testbench
# vsim +nowarnTSCALE -novopt work.testbench 
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
add wave sim:/testbench/U_fir/U_ram_fir/*
run
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
run -all
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
add wave  \
sim:/testbench/U_fir/U_ram_fir/dra_W
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave  \
sim:/testbench/U_fir/U_ram_fir/k_cnt_d1R
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave -position 4  sim:/testbench/U_fir/U_ram_fir/din_d1R
add wave -position 5  sim:/testbench/U_fir/U_ram_fir/din_d2R
add wave -position 4  sim:/testbench/U_fir/U_ram_fir/den_d1R
add wave -position 5  sim:/testbench/U_fir/U_ram_fir/den_d2R
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave -position 9  sim:/testbench/U_fir/U_ram_fir/k_valid_W
add wave -position 10  sim:/testbench/U_fir/U_ram_fir/k_d1R_valid_W
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave -position 8  sim:/testbench/U_fir/U_ram_fir/d_st_W
add wave -position 9  sim:/testbench/U_fir/U_ram_fir/d_ed_W
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
add wave  \
sim:/testbench/U_fir/U_ram_fir/U_pe/START \
sim:/testbench/U_fir/U_ram_fir/U_pe/END \
sim:/testbench/U_fir/U_ram_fir/U_pe/IN1 \
sim:/testbench/U_fir/U_ram_fir/U_pe/IN2 \
sim:/testbench/U_fir/U_ram_fir/U_pe/DEN \
sim:/testbench/U_fir/U_ram_fir/U_pe/SOV \
sim:/testbench/U_fir/U_ram_fir/U_pe/SUM
# Add Signal sim:/testbench/U_fir/U_ram_fir/U_pe/START 
when -label sim:/testbench/U_fir/U_ram_fir/U_pe/START sim:/testbench/U_fir/U_ram_fir/U_pe/START {echo {Break on sim:/testbench/U_fir/U_ram_fir/U_pe/START} ; stop}
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break on sim:/testbench/U_fir/U_ram_fir/U_pe/START 
# Simulation stop requested.
run -all
# Break on sim:/testbench/U_fir/U_ram_fir/U_pe/START 
# Simulation stop requested.
run -all
# Break on sim:/testbench/U_fir/U_ram_fir/U_pe/START 
# Simulation stop requested.
run -all
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
add wave -position 33  sim:/testbench/U_fir/U_ram_fir/U_pe/in1_R1
add wave -position 34  sim:/testbench/U_fir/U_ram_fir/U_pe/in1_R2
add wave -position 35  sim:/testbench/U_fir/U_ram_fir/U_pe/in2_R1
add wave -position 36  sim:/testbench/U_fir/U_ram_fir/U_pe/in2_R2
add wave -position 37  sim:/testbench/U_fir/U_ram_fir/U_pe/p_W
add wave -position 38  sim:/testbench/U_fir/U_ram_fir/U_pe/p_R
add wave -position 39  sim:/testbench/U_fir/U_ram_fir/U_pe/round_R
add wave -position 40  sim:/testbench/U_fir/U_ram_fir/U_pe/sum_R1
add wave -position 41  sim:/testbench/U_fir/U_ram_fir/U_pe/sum_R2
add wave -position 40  sim:/testbench/U_fir/U_ram_fir/U_pe/den_R1
add wave -position 41  sim:/testbench/U_fir/U_ram_fir/U_pe/den_R2
add wave -position 42  sim:/testbench/U_fir/U_ram_fir/U_pe/den_R3
add wave -position 43  sim:/testbench/U_fir/U_ram_fir/U_pe/den_R4
add wave -position 44  sim:/testbench/U_fir/U_ram_fir/U_pe/den_R5
add wave -position 45  sim:/testbench/U_fir/U_ram_fir/U_pe/start_R1
add wave -position 46  sim:/testbench/U_fir/U_ram_fir/U_pe/start_R2
add wave -position 47  sim:/testbench/U_fir/U_ram_fir/U_pe/start_R3
add wave -position 48  sim:/testbench/U_fir/U_ram_fir/U_pe/start_R4
add wave -position 49  sim:/testbench/U_fir/U_ram_fir/U_pe/start_R5
add wave -position 50  sim:/testbench/U_fir/U_ram_fir/U_pe/end_R1
add wave -position 51  sim:/testbench/U_fir/U_ram_fir/U_pe/end_R2
add wave -position 52  sim:/testbench/U_fir/U_ram_fir/U_pe/end_R3
add wave -position 53  sim:/testbench/U_fir/U_ram_fir/U_pe/end_R4
add wave -position 54  sim:/testbench/U_fir/U_ram_fir/U_pe/end_R5
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave -position 38  sim:/testbench/U_fir/U_ram_fir/U_pe/round_W
add wave -position 39  sim:/testbench/U_fir/U_ram_fir/U_pe/p_sign_W
# Causality operation skipped due to absense of debug database file
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
add wave -position 3  sim:/testbench/U_dut_in/send_cnt_R
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Warning: (vsim-3015) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(107): [PCDPC] - Port size (8 or 8) does not match connection size (16) for port 'RD'. The port definition is at: D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/DUT_IN_ROM.v(11).
#         Region: /testbench/U_dut_in/U_rom
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Warning: (vsim-3015) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(107): [PCDPC] - Port size (8 or 8) does not match connection size (16) for port 'RD'. The port definition is at: D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/DUT_IN_ROM.v(11).
#         Region: /testbench/U_dut_in/U_rom
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
restart
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f {} -noaddress -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f {} -noaddress -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
add wave -position end  sim:/testbench/U_dut_out/DUTOV
add wave -position end  sim:/testbench/U_dut_out/DUTOUT
add wave -position end  sim:/testbench/U_dut_out/CNT
add wave -position end  sim:/testbench/U_dut_out/dutov_d1R
add wave -position end  sim:/testbench/U_dut_out/wa_cnt_R1
add wave -position end  sim:/testbench/U_dut_out/wa_cnt_R2
add wave -position end  sim:/testbench/U_dut_out/dut_outR
add wave -position end  sim:/testbench/U_dut_out/wa_W
add wave -position end  sim:/testbench/U_dut_out/we_W
restart
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f {} -noaddress -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Warning: (vsim-3015) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(107): [PCDPC] - Port size (16 or 16) does not match connection size (18) for port 'RD'. The port definition is at: D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/DUT_IN_ROM.v(11).
#         Region: /testbench/U_dut_in/U_rom
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Warning: (vsim-3015) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(107): [PCDPC] - Port size (16 or 16) does not match connection size (18) for port 'RD'. The port definition is at: D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/DUT_IN_ROM.v(11).
#         Region: /testbench/U_dut_in/U_rom
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v failed with 1 errors.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Warning in wave window restart: (vish-4014) No objects found matching '/testbench/U_fir/U_ram_fir/U_pe/p_sign_W'. 
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module fir_dpram().RAMInit()called @ 0
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v failed with 1 errors.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 1 failed with 1 error. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Error: (vsim-PLI-3069) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(249): $fwrite : Argument number 1 is invalid.
#         Region: /testbench
# ** Error: (vsim-PLI-3069) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(255): $fwrite : Argument number 1 is invalid.
#         Region: /testbench
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
 vsim -novopt +nowarnTSCALE work.testbench
# vsim +nowarnTSCALE -novopt work.testbench 
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Error: (vsim-PLI-3069) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(249): $fwrite : Argument number 1 is invalid.
#         Region: /testbench
# ** Error: (vsim-PLI-3069) D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/dut_in_out.v(255): $fwrite : Argument number 1 is invalid.
#         Region: /testbench
# Error loading design
# A time value could not be extracted from the current line
# Compile of DUT_IN_ROM.v was successful.
# Compile of ram_fir.v was successful.
# Compile of testbench.v was successful.
# Compile of dut_in_out.v was successful.
# Compile of fir1_coeff_rom.v was successful.
# 5 compiles, 0 failed with no errors. 
 vsim -novopt +nowarnTSCALE work.testbench
# vsim +nowarnTSCALE -novopt work.testbench 
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_inst
# Loading work.fir_inst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir
# Loading work.ram_fir
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.ram_fir_pe
# Loading work.ram_fir_pe
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir1_coeff_rom
# Loading work.fir1_coeff_rom
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.fir_dpram
# Loading work.fir_dpram
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
