library verilog;
use verilog.vl_types.all;
entity ram_fir is
    generic(
        INWL            : integer := 16;
        OUTWL           : integer := 20;
        AWL             : integer := 4;
        NCOEF           : integer := 12;
        C2Q             : integer := 2
    );
    port(
        RST             : in     vl_logic;
        CLK             : in     vl_logic;
        DIN             : in     vl_logic_vector;
        DEN             : in     vl_logic;
        FOUT            : out    vl_logic_vector;
        FOV             : out    vl_logic;
        CLKOUT          : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of INWL : constant is 1;
    attribute mti_svvh_generic_type of OUTWL : constant is 1;
    attribute mti_svvh_generic_type of AWL : constant is 1;
    attribute mti_svvh_generic_type of NCOEF : constant is 1;
    attribute mti_svvh_generic_type of C2Q : constant is 1;
end ram_fir;
