library verilog;
use verilog.vl_types.all;
entity dut_in_data is
    generic(
        SEND_DATA_NUM   : integer := 0;
        SEND_ROM_AWL    : integer := 0;
        SEND_CYCLE      : integer := 0;
        SEND_MODE       : integer := 0;
        DUT_INWL        : integer := 0;
        DUT_OUTWL       : integer := 0;
        CYCLE_CNT_WL    : integer := 16;
        SEND_CNT_WL     : integer := 16;
        MAX_SEND_CNT_VAL: vl_notype;
        MAX_CYCLE_CNT   : vl_notype
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DUT_DINEN       : out    vl_logic;
        DUT_DIN         : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of SEND_DATA_NUM : constant is 1;
    attribute mti_svvh_generic_type of SEND_ROM_AWL : constant is 1;
    attribute mti_svvh_generic_type of SEND_CYCLE : constant is 1;
    attribute mti_svvh_generic_type of SEND_MODE : constant is 1;
    attribute mti_svvh_generic_type of DUT_INWL : constant is 1;
    attribute mti_svvh_generic_type of DUT_OUTWL : constant is 1;
    attribute mti_svvh_generic_type of CYCLE_CNT_WL : constant is 1;
    attribute mti_svvh_generic_type of SEND_CNT_WL : constant is 1;
    attribute mti_svvh_generic_type of MAX_SEND_CNT_VAL : constant is 3;
    attribute mti_svvh_generic_type of MAX_CYCLE_CNT : constant is 3;
end dut_in_data;
