library verilog;
use verilog.vl_types.all;
entity testbench is
    generic(
        CLK_PERIOD      : integer := 1;
        CLK_PERIOD_HALF : vl_notype;
        SEND_DATA_NUM   : integer := 1024;
        SEND_ROM_AWL    : integer := 10;
        SEND_CYCLE      : integer := 20;
        SEND_MODE       : integer := 0;
        DUT_INWL        : integer := 16;
        DUT_OUTWL       : integer := 20;
        TIME_RUN        : vl_notype
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of CLK_PERIOD : constant is 1;
    attribute mti_svvh_generic_type of CLK_PERIOD_HALF : constant is 3;
    attribute mti_svvh_generic_type of SEND_DATA_NUM : constant is 1;
    attribute mti_svvh_generic_type of SEND_ROM_AWL : constant is 1;
    attribute mti_svvh_generic_type of SEND_CYCLE : constant is 1;
    attribute mti_svvh_generic_type of SEND_MODE : constant is 1;
    attribute mti_svvh_generic_type of DUT_INWL : constant is 1;
    attribute mti_svvh_generic_type of DUT_OUTWL : constant is 1;
    attribute mti_svvh_generic_type of TIME_RUN : constant is 3;
end testbench;
