library verilog;
use verilog.vl_types.all;
entity DUT_IN_ROM is
    port(
        CLK             : in     vl_logic;
        RA              : in     vl_logic_vector(9 downto 0);
        RD              : out    vl_logic_vector(7 downto 0)
    );
end DUT_IN_ROM;
