datasheet for JTAG_MM

JTAG_MM |

2015.06.08.21:09:52 | Datasheet

Overview

clk_0 | JTAG_MM

All Components
POUT altera_avalon_pio 13.1
PIN altera_avalon_pio 13.1
Memory Map

| master_0
master
POUT |
s1 | 0x00000010
PIN |
s1 | 0x00000000

## clk_0

clock_source v13.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## master_0

altera_jtag_avalon_master v13.1

clk_0 | clk_reset | master_0
clk_reset
clk
clk
|  | master | POUT
|  | s1
|  | master | PIN
|  | s1

## Parameters

USE_PLI | 0
PLI_PORT | 50000
COMPONENT_CLOCK | 0
FAST_VER | 0
FIFO_DEPTHS | 2
AUTO_DEVICE_FAMILY | CYCLONEIII
AUTO_DEVICE | EP3C16F484C6
deviceFamily | Cyclone III
generateLegacySim | false

## Software Assignments

(none)

## POUT

altera_avalon_pio v13.1

clk_0 | clk_reset | POUT
reset
clk
clk
master_0 | master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 8
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 8
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## PIN

altera_avalon_pio v13.1

clk_0 | clk_reset | PIN
reset
clk
clk
master_0 | master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 8
clockRate | 50000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 8
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

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