|top_sin_wave
CLK => CLK.IN6
BUTUP => butup_W.IN1
BUTDOWN => butdown_W.IN1
BUTRST => butrst_W.IN1
CLKOUT <= dds_core_sin:U_DDS.CLKOUT
SINOUT[0] <= dds_core_sin:U_DDS.SINOUT
SINOUT[1] <= dds_core_sin:U_DDS.SINOUT
SINOUT[2] <= dds_core_sin:U_DDS.SINOUT
SINOUT[3] <= dds_core_sin:U_DDS.SINOUT
SINOUT[4] <= dds_core_sin:U_DDS.SINOUT
SINOUT[5] <= dds_core_sin:U_DDS.SINOUT
SINOUT[6] <= dds_core_sin:U_DDS.SINOUT
SINOUT[7] <= dds_core_sin:U_DDS.SINOUT
SINOUT[8] <= dds_core_sin:U_DDS.SINOUT
SINOUT[9] <= dds_core_sin:U_DDS.SINOUT
SINOUT[10] <= dds_core_sin:U_DDS.SINOUT
SINOUT[11] <= dds_core_sin:U_DDS.SINOUT


|top_sin_wave|powerup_reset:U_PURST
CLK => counterR[0].CLK
CLK => counterR[1].CLK
CLK => counterR[2].CLK
CLK => counterR[3].CLK
CLK => counterR[4].CLK
CLK => counterR[5].CLK
CLK => counterR[6].CLK
CLK => counterR[7].CLK
CLK => counterR[8].CLK
CLK => counterR[9].CLK
CLK => counterR[10].CLK
CLK => counterR[11].CLK
CLK => counterR[12].CLK
CLK => counterR[13].CLK
CLK => counterR[14].CLK
CLK => counterR[15].CLK
CLK => counterR[16].CLK
CLK => counterR[17].CLK
CLK => counterR[18].CLK
CLK => counterR[19].CLK
CLK => counterR[20].CLK
CLK => counterR[21].CLK
CLK => counterR[22].CLK
CLK => counterR[23].CLK
CLK => counterR[24].CLK
CLK => counterR[25].CLK
CLK => counterR[26].CLK
CLK => counterR[27].CLK
CLK => counterR[28].CLK
CLK => counterR[29].CLK
CLK => counterR[30].CLK
CLK => counterR[31].CLK
RSTOUT <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|button_in_out:U_BUTUP
CLK => buttonOutR.CLK
CLK => counterR[0].CLK
CLK => counterR[1].CLK
CLK => counterR[2].CLK
CLK => counterR[3].CLK
CLK => counterR[4].CLK
CLK => counterR[5].CLK
CLK => counterR[6].CLK
CLK => counterR[7].CLK
CLK => counterR[8].CLK
CLK => counterR[9].CLK
CLK => counterR[10].CLK
CLK => counterR[11].CLK
CLK => counterR[12].CLK
CLK => counterR[13].CLK
CLK => counterR[14].CLK
CLK => counterR[15].CLK
CLK => counterR[16].CLK
CLK => counterR[17].CLK
CLK => counterR[18].CLK
CLK => counterR[19].CLK
CLK => buttonIn3R.CLK
CLK => buttonIn2R.CLK
CLK => buttonIn1R.CLK
CLK => buttonIn0R.CLK
CLK => button_in_d2R.CLK
CLK => button_in_d1R.CLK
IN => button_in_d1R.DATAIN
OUT <= buttonOutR.DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|button_in_out:U_BUTDOWN
CLK => buttonOutR.CLK
CLK => counterR[0].CLK
CLK => counterR[1].CLK
CLK => counterR[2].CLK
CLK => counterR[3].CLK
CLK => counterR[4].CLK
CLK => counterR[5].CLK
CLK => counterR[6].CLK
CLK => counterR[7].CLK
CLK => counterR[8].CLK
CLK => counterR[9].CLK
CLK => counterR[10].CLK
CLK => counterR[11].CLK
CLK => counterR[12].CLK
CLK => counterR[13].CLK
CLK => counterR[14].CLK
CLK => counterR[15].CLK
CLK => counterR[16].CLK
CLK => counterR[17].CLK
CLK => counterR[18].CLK
CLK => counterR[19].CLK
CLK => buttonIn3R.CLK
CLK => buttonIn2R.CLK
CLK => buttonIn1R.CLK
CLK => buttonIn0R.CLK
CLK => button_in_d2R.CLK
CLK => button_in_d1R.CLK
IN => button_in_d1R.DATAIN
OUT <= buttonOutR.DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|button_in_out:U_BUTRST
CLK => buttonOutR.CLK
CLK => counterR[0].CLK
CLK => counterR[1].CLK
CLK => counterR[2].CLK
CLK => counterR[3].CLK
CLK => counterR[4].CLK
CLK => counterR[5].CLK
CLK => counterR[6].CLK
CLK => counterR[7].CLK
CLK => counterR[8].CLK
CLK => counterR[9].CLK
CLK => counterR[10].CLK
CLK => counterR[11].CLK
CLK => counterR[12].CLK
CLK => counterR[13].CLK
CLK => counterR[14].CLK
CLK => counterR[15].CLK
CLK => counterR[16].CLK
CLK => counterR[17].CLK
CLK => counterR[18].CLK
CLK => counterR[19].CLK
CLK => buttonIn3R.CLK
CLK => buttonIn2R.CLK
CLK => buttonIn1R.CLK
CLK => buttonIn0R.CLK
CLK => button_in_d2R.CLK
CLK => button_in_d1R.CLK
IN => button_in_d1R.DATAIN
OUT <= buttonOutR.DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|generate_freq_word:U_GFQWD
CLK => FWEN~reg0.CLK
CLK => FQWD[0]~reg0.CLK
CLK => FQWD[1]~reg0.CLK
CLK => FQWD[2]~reg0.CLK
CLK => FQWD[3]~reg0.CLK
CLK => FQWD[4]~reg0.CLK
CLK => FQWD[5]~reg0.CLK
CLK => FQWD[6]~reg0.CLK
CLK => FQWD[7]~reg0.CLK
CLK => FQWD[8]~reg0.CLK
CLK => FQWD[9]~reg0.CLK
CLK => FQWD[10]~reg0.CLK
CLK => FQWD[11]~reg0.CLK
CLK => FQWD[12]~reg0.CLK
CLK => FQWD[13]~reg0.CLK
CLK => FQWD[14]~reg0.CLK
CLK => FQWD[15]~reg0.CLK
CLK => FQWD[16]~reg0.CLK
CLK => FQWD[17]~reg0.CLK
CLK => FQWD[18]~reg0.CLK
CLK => FQWD[19]~reg0.CLK
CLK => FQWD[20]~reg0.CLK
CLK => FQWD[21]~reg0.CLK
CLK => FQWD[22]~reg0.CLK
CLK => FQWD[23]~reg0.CLK
CLK => FQWD[24]~reg0.CLK
CLK => FQWD[25]~reg0.CLK
CLK => FQWD[26]~reg0.CLK
CLK => FQWD[27]~reg0.CLK
CLK => FQWD[28]~reg0.CLK
CLK => FQWD[29]~reg0.CLK
CLK => FQWD[30]~reg0.CLK
CLK => FQWD[31]~reg0.CLK
CLK => butdown_enR.CLK
CLK => butup_enR.CLK
CLK => butdown_d1R.CLK
CLK => butup_d1R.CLK
RST => FWEN~reg0.PRESET
RST => FQWD[0]~reg0.PRESET
RST => FQWD[1]~reg0.ACLR
RST => FQWD[2]~reg0.ACLR
RST => FQWD[3]~reg0.ACLR
RST => FQWD[4]~reg0.PRESET
RST => FQWD[5]~reg0.ACLR
RST => FQWD[6]~reg0.PRESET
RST => FQWD[7]~reg0.ACLR
RST => FQWD[8]~reg0.ACLR
RST => FQWD[9]~reg0.ACLR
RST => FQWD[10]~reg0.ACLR
RST => FQWD[11]~reg0.PRESET
RST => FQWD[12]~reg0.PRESET
RST => FQWD[13]~reg0.PRESET
RST => FQWD[14]~reg0.ACLR
RST => FQWD[15]~reg0.PRESET
RST => FQWD[16]~reg0.ACLR
RST => FQWD[17]~reg0.PRESET
RST => FQWD[18]~reg0.PRESET
RST => FQWD[19]~reg0.PRESET
RST => FQWD[20]~reg0.PRESET
RST => FQWD[21]~reg0.ACLR
RST => FQWD[22]~reg0.ACLR
RST => FQWD[23]~reg0.ACLR
RST => FQWD[24]~reg0.PRESET
RST => FQWD[25]~reg0.ACLR
RST => FQWD[26]~reg0.PRESET
RST => FQWD[27]~reg0.ACLR
RST => FQWD[28]~reg0.ACLR
RST => FQWD[29]~reg0.ACLR
RST => FQWD[30]~reg0.ACLR
RST => FQWD[31]~reg0.ACLR
RST => butdown_enR.ACLR
RST => butup_enR.ACLR
RST => butdown_d1R.ACLR
RST => butup_d1R.ACLR
BUTUP => always0.IN1
BUTUP => butup_d1R.DATAIN
BUTDOWN => always0.IN1
BUTDOWN => butdown_d1R.DATAIN
FQWD[0] <= FQWD[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[1] <= FQWD[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[2] <= FQWD[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[3] <= FQWD[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[4] <= FQWD[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[5] <= FQWD[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[6] <= FQWD[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[7] <= FQWD[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[8] <= FQWD[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[9] <= FQWD[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[10] <= FQWD[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[11] <= FQWD[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[12] <= FQWD[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[13] <= FQWD[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[14] <= FQWD[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[15] <= FQWD[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[16] <= FQWD[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[17] <= FQWD[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[18] <= FQWD[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[19] <= FQWD[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[20] <= FQWD[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[21] <= FQWD[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[22] <= FQWD[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[23] <= FQWD[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[24] <= FQWD[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[25] <= FQWD[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[26] <= FQWD[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[27] <= FQWD[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[28] <= FQWD[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[29] <= FQWD[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[30] <= FQWD[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FQWD[31] <= FQWD[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
FWEN <= FWEN~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|dds_core_sin:U_DDS
CLK => CLK.IN1
RST => sinout_R[0].ACLR
RST => sinout_R[1].ACLR
RST => sinout_R[2].ACLR
RST => sinout_R[3].ACLR
RST => sinout_R[4].ACLR
RST => sinout_R[5].ACLR
RST => sinout_R[6].ACLR
RST => sinout_R[7].ACLR
RST => sinout_R[8].ACLR
RST => sinout_R[9].ACLR
RST => sinout_R[10].ACLR
RST => sinout_R[11].ACLR
RST => addr_R[0].ACLR
RST => addr_R[1].ACLR
RST => addr_R[2].ACLR
RST => addr_R[3].ACLR
RST => addr_R[4].ACLR
RST => addr_R[5].ACLR
RST => addr_R[6].ACLR
RST => addr_R[7].ACLR
RST => addr_R[8].ACLR
RST => addr_R[9].ACLR
RST => acc_R[0].ACLR
RST => acc_R[1].ACLR
RST => acc_R[2].ACLR
RST => acc_R[3].ACLR
RST => acc_R[4].ACLR
RST => acc_R[5].ACLR
RST => acc_R[6].ACLR
RST => acc_R[7].ACLR
RST => acc_R[8].ACLR
RST => acc_R[9].ACLR
RST => acc_R[10].ACLR
RST => acc_R[11].ACLR
RST => acc_R[12].ACLR
RST => acc_R[13].ACLR
RST => acc_R[14].ACLR
RST => acc_R[15].ACLR
RST => acc_R[16].ACLR
RST => acc_R[17].ACLR
RST => acc_R[18].ACLR
RST => acc_R[19].ACLR
RST => acc_R[20].ACLR
RST => acc_R[21].ACLR
RST => acc_R[22].ACLR
RST => acc_R[23].ACLR
RST => acc_R[24].ACLR
RST => acc_R[25].ACLR
RST => acc_R[26].ACLR
RST => acc_R[27].ACLR
RST => acc_R[28].ACLR
RST => acc_R[29].ACLR
RST => acc_R[30].ACLR
RST => acc_R[31].ACLR
RST => fwin_R[0].ACLR
RST => fwin_R[1].ACLR
RST => fwin_R[2].ACLR
RST => fwin_R[3].ACLR
RST => fwin_R[4].ACLR
RST => fwin_R[5].ACLR
RST => fwin_R[6].ACLR
RST => fwin_R[7].ACLR
RST => fwin_R[8].ACLR
RST => fwin_R[9].ACLR
RST => fwin_R[10].ACLR
RST => fwin_R[11].ACLR
RST => fwin_R[12].ACLR
RST => fwin_R[13].ACLR
RST => fwin_R[14].ACLR
RST => fwin_R[15].ACLR
RST => fwin_R[16].ACLR
RST => fwin_R[17].ACLR
RST => fwin_R[18].ACLR
RST => fwin_R[19].ACLR
RST => fwin_R[20].ACLR
RST => fwin_R[21].ACLR
RST => fwin_R[22].ACLR
RST => fwin_R[23].ACLR
RST => fwin_R[24].ACLR
RST => fwin_R[25].ACLR
RST => fwin_R[26].ACLR
RST => fwin_R[27].ACLR
RST => fwin_R[28].ACLR
RST => fwin_R[29].ACLR
RST => fwin_R[30].ACLR
RST => fwin_R[31].ACLR
FWEN => fwin_R[31].ENA
FWEN => fwin_R[30].ENA
FWEN => fwin_R[29].ENA
FWEN => fwin_R[28].ENA
FWEN => fwin_R[27].ENA
FWEN => fwin_R[26].ENA
FWEN => fwin_R[25].ENA
FWEN => fwin_R[24].ENA
FWEN => fwin_R[23].ENA
FWEN => fwin_R[22].ENA
FWEN => fwin_R[21].ENA
FWEN => fwin_R[20].ENA
FWEN => fwin_R[19].ENA
FWEN => fwin_R[18].ENA
FWEN => fwin_R[17].ENA
FWEN => fwin_R[16].ENA
FWEN => fwin_R[15].ENA
FWEN => fwin_R[14].ENA
FWEN => fwin_R[13].ENA
FWEN => fwin_R[12].ENA
FWEN => fwin_R[11].ENA
FWEN => fwin_R[10].ENA
FWEN => fwin_R[9].ENA
FWEN => fwin_R[8].ENA
FWEN => fwin_R[7].ENA
FWEN => fwin_R[6].ENA
FWEN => fwin_R[5].ENA
FWEN => fwin_R[4].ENA
FWEN => fwin_R[3].ENA
FWEN => fwin_R[2].ENA
FWEN => fwin_R[1].ENA
FWEN => fwin_R[0].ENA
FWIN[0] => fwin_R[0].DATAIN
FWIN[1] => fwin_R[1].DATAIN
FWIN[2] => fwin_R[2].DATAIN
FWIN[3] => fwin_R[3].DATAIN
FWIN[4] => fwin_R[4].DATAIN
FWIN[5] => fwin_R[5].DATAIN
FWIN[6] => fwin_R[6].DATAIN
FWIN[7] => fwin_R[7].DATAIN
FWIN[8] => fwin_R[8].DATAIN
FWIN[9] => fwin_R[9].DATAIN
FWIN[10] => fwin_R[10].DATAIN
FWIN[11] => fwin_R[11].DATAIN
FWIN[12] => fwin_R[12].DATAIN
FWIN[13] => fwin_R[13].DATAIN
FWIN[14] => fwin_R[14].DATAIN
FWIN[15] => fwin_R[15].DATAIN
FWIN[16] => fwin_R[16].DATAIN
FWIN[17] => fwin_R[17].DATAIN
FWIN[18] => fwin_R[18].DATAIN
FWIN[19] => fwin_R[19].DATAIN
FWIN[20] => fwin_R[20].DATAIN
FWIN[21] => fwin_R[21].DATAIN
FWIN[22] => fwin_R[22].DATAIN
FWIN[23] => fwin_R[23].DATAIN
FWIN[24] => fwin_R[24].DATAIN
FWIN[25] => fwin_R[25].DATAIN
FWIN[26] => fwin_R[26].DATAIN
FWIN[27] => fwin_R[27].DATAIN
FWIN[28] => fwin_R[28].DATAIN
FWIN[29] => fwin_R[29].DATAIN
FWIN[30] => fwin_R[30].DATAIN
FWIN[31] => fwin_R[31].DATAIN
CLKOUT <= CLK.DB_MAX_OUTPUT_PORT_TYPE
SINOUT[0] <= sinout_R[0].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[1] <= sinout_R[1].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[2] <= sinout_R[2].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[3] <= sinout_R[3].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[4] <= sinout_R[4].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[5] <= sinout_R[5].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[6] <= sinout_R[6].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[7] <= sinout_R[7].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[8] <= sinout_R[8].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[9] <= sinout_R[9].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[10] <= sinout_R[10].DB_MAX_OUTPUT_PORT_TYPE
SINOUT[11] <= sinout_R[11].DB_MAX_OUTPUT_PORT_TYPE


|top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom
CLK => RD[0]~reg0.CLK
CLK => RD[1]~reg0.CLK
CLK => RD[2]~reg0.CLK
CLK => RD[3]~reg0.CLK
CLK => RD[4]~reg0.CLK
CLK => RD[5]~reg0.CLK
CLK => RD[6]~reg0.CLK
CLK => RD[7]~reg0.CLK
CLK => RD[8]~reg0.CLK
CLK => RD[9]~reg0.CLK
CLK => RD[10]~reg0.CLK
CLK => RD[11]~reg0.CLK
RA[0] => Ram0.RADDR
RA[1] => Ram0.RADDR1
RA[2] => Ram0.RADDR2
RA[3] => Ram0.RADDR3
RA[4] => Ram0.RADDR4
RA[5] => Ram0.RADDR5
RA[6] => Ram0.RADDR6
RA[7] => Ram0.RADDR7
RA[8] => Ram0.RADDR8
RA[9] => Ram0.RADDR9
RD[0] <= RD[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[1] <= RD[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[2] <= RD[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[3] <= RD[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[4] <= RD[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[5] <= RD[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[6] <= RD[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[7] <= RD[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[8] <= RD[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[9] <= RD[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[10] <= RD[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RD[11] <= RD[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE


