Analysis & Synthesis report for top_sin_wave
Sun Jun 07 20:49:14 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Registers Packed Into Inferred Megafunctions
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
 15. Source assignments for dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated
 16. Parameter Settings for User Entity Instance: powerup_reset:U_PURST
 17. Parameter Settings for User Entity Instance: button_in_out:U_BUTUP
 18. Parameter Settings for User Entity Instance: button_in_out:U_BUTDOWN
 19. Parameter Settings for User Entity Instance: button_in_out:U_BUTRST
 20. Parameter Settings for User Entity Instance: generate_freq_word:U_GFQWD
 21. Parameter Settings for User Entity Instance: dds_core_sin:U_DDS
 22. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 23. Parameter Settings for Inferred Entity Instance: dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0
 24. altsyncram Parameter Settings by Entity Instance
 25. SignalTap II Logic Analyzer Settings
 26. Elapsed Time Per Partition
 27. Connections to In-System Debugging Instance "auto_signaltap_0"
 28. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jun 07 20:49:14 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; top_sin_wave                                ;
; Top-level Entity Name              ; top_sin_wave                                ;
; Family                             ; Cyclone III                                 ;
; Total logic elements               ; 1,574                                       ;
;     Total combinational functions  ; 919                                         ;
;     Dedicated logic registers      ; 1,183                                       ;
; Total registers                    ; 1183                                        ;
; Total pins                         ; 17                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 192,512                                     ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C16F484C6       ;                    ;
; Top-level entity name                                                      ; top_sin_wave       ; top_sin_wave       ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Optimization Technique                                                     ; Area               ; Balanced           ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; Off                ; Off                ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                              ;
+----------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path                   ; Used in Netlist ; File Type                                             ; File Name with Absolute Path                                                                               ; Library ;
+----------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+---------+
; ../src/powerup_reset.v                             ; yes             ; User Verilog HDL File                                 ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/powerup_reset.v                                         ;         ;
; ../src/top_sin_wave.v                              ; yes             ; User Verilog HDL File                                 ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v                                          ;         ;
; ../src/button.v                                    ; yes             ; User Verilog HDL File                                 ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/button.v                                                ;         ;
; ../src/dds_core.v                                  ; yes             ; User Verilog HDL File                                 ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/dds_core.v                                              ;         ;
; ../src/DDS_CORE_ROM.v                              ; yes             ; User Verilog HDL File                                 ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/DDS_CORE_ROM.v                                          ;         ;
; sld_signaltap.vhd                                  ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/sld_signaltap.vhd                                           ;         ;
; sld_signaltap_impl.vhd                             ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd                                      ;         ;
; sld_ela_control.vhd                                ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_ela_control.vhd                                         ;         ;
; lpm_shiftreg.tdf                                   ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf                                            ;         ;
; lpm_constant.inc                                   ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc                                            ;         ;
; dffeea.inc                                         ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/dffeea.inc                                                  ;         ;
; aglobal131.inc                                     ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                              ;         ;
; sld_mbpmg.vhd                                      ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_mbpmg.vhd                                               ;         ;
; sld_ela_trigger_flow_mgr.vhd                       ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd                                ;         ;
; sld_buffer_manager.vhd                             ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd                                      ;         ;
; altsyncram.tdf                                     ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf                                              ;         ;
; stratix_ram_block.inc                              ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc                                       ;         ;
; lpm_mux.inc                                        ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc                                                 ;         ;
; lpm_decode.inc                                     ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc                                              ;         ;
; a_rdenreg.inc                                      ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc                                               ;         ;
; altrom.inc                                         ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc                                                  ;         ;
; altram.inc                                         ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc                                                  ;         ;
; altdpram.inc                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                                ;         ;
; db/altsyncram_nq14.tdf                             ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/altsyncram_nq14.tdf                             ;         ;
; altdpram.tdf                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.tdf                                                ;         ;
; memmodes.inc                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/others/maxplus2/memmodes.inc                                              ;         ;
; a_hdffe.inc                                        ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/a_hdffe.inc                                                 ;         ;
; alt_le_rden_reg.inc                                ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/alt_le_rden_reg.inc                                         ;         ;
; altsyncram.inc                                     ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.inc                                              ;         ;
; lpm_mux.tdf                                        ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.tdf                                                 ;         ;
; muxlut.inc                                         ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/muxlut.inc                                                  ;         ;
; bypassff.inc                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc                                                ;         ;
; altshift.inc                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc                                                ;         ;
; db/mux_krc.tdf                                     ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/mux_krc.tdf                                     ;         ;
; lpm_decode.tdf                                     ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.tdf                                              ;         ;
; declut.inc                                         ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/declut.inc                                                  ;         ;
; lpm_compare.inc                                    ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc                                             ;         ;
; db/decode_4uf.tdf                                  ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/decode_4uf.tdf                                  ;         ;
; lpm_counter.tdf                                    ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.tdf                                             ;         ;
; lpm_add_sub.inc                                    ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                             ;         ;
; cmpconst.inc                                       ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/cmpconst.inc                                                ;         ;
; lpm_counter.inc                                    ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc                                             ;         ;
; alt_counter_stratix.inc                            ; yes             ; Megafunction                                          ; c:/altera/13.1/quartus/libraries/megafunctions/alt_counter_stratix.inc                                     ;         ;
; db/cntr_9fi.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_9fi.tdf                                    ;         ;
; db/cmpr_jfc.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_jfc.tdf                                    ;         ;
; db/cntr_d8j.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_d8j.tdf                                    ;         ;
; db/cntr_7fi.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_7fi.tdf                                    ;         ;
; db/cmpr_ifc.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_ifc.tdf                                    ;         ;
; db/cntr_p1j.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_p1j.tdf                                    ;         ;
; db/cmpr_efc.tdf                                    ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_efc.tdf                                    ;         ;
; sld_rom_sr.vhd                                     ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_rom_sr.vhd                                              ;         ;
; sld_hub.vhd                                        ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_hub.vhd                                                 ;         ;
; sld_jtag_hub.vhd                                   ; yes             ; Encrypted Megafunction                                ; c:/altera/13.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd                                            ;         ;
; db/altsyncram_k581.tdf                             ; yes             ; Auto-Generated Megafunction                           ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/altsyncram_k581.tdf                             ;         ;
; db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif ; yes             ; Auto-Generated Auto-Found Memory Initialization File  ; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif ;         ;
+----------------------------------------------------+-----------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+---------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Estimated Total logic elements              ; 1,574     ;
;                                             ;           ;
; Total combinational functions               ; 919       ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 360       ;
;     -- 3 input functions                    ; 215       ;
;     -- <=2 input functions                  ; 344       ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 680       ;
;     -- arithmetic mode                      ; 239       ;
;                                             ;           ;
; Total registers                             ; 1183      ;
;     -- Dedicated logic registers            ; 1183      ;
;     -- I/O registers                        ; 0         ;
;                                             ;           ;
; I/O pins                                    ; 17        ;
; Total memory bits                           ; 192512    ;
; Embedded Multiplier 9-bit elements          ; 0         ;
; Maximum fan-out node                        ; CLK~input ;
; Maximum fan-out                             ; 760       ;
; Total fan-out                               ; 7761      ;
; Average fan-out                             ; 3.53      ;
+---------------------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                              ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                ; Library Name ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |top_sin_wave                                                                                           ; 919 (2)           ; 1183 (0)     ; 192512      ; 0            ; 0       ; 0         ; 17   ; 0            ; |top_sin_wave                                                                                                                                                                                                                                                                                                                                      ; work         ;
;    |button_in_out:U_BUTDOWN|                                                                            ; 29 (29)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|button_in_out:U_BUTDOWN                                                                                                                                                                                                                                                                                                              ; work         ;
;    |button_in_out:U_BUTRST|                                                                             ; 18 (18)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|button_in_out:U_BUTRST                                                                                                                                                                                                                                                                                                               ; work         ;
;    |button_in_out:U_BUTUP|                                                                              ; 3 (3)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|button_in_out:U_BUTUP                                                                                                                                                                                                                                                                                                                ; work         ;
;    |dds_core_sin:U_DDS|                                                                                 ; 45 (45)           ; 86 (86)      ; 12288       ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|dds_core_sin:U_DDS                                                                                                                                                                                                                                                                                                                   ; work         ;
;       |DDS_CORE_ROM:u_sinrom|                                                                           ; 0 (0)             ; 0 (0)        ; 12288       ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom                                                                                                                                                                                                                                                                                             ; work         ;
;          |altsyncram:Ram0_rtl_0|                                                                        ; 0 (0)             ; 0 (0)        ; 12288       ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0                                                                                                                                                                                                                                                                       ; work         ;
;             |altsyncram_k581:auto_generated|                                                            ; 0 (0)             ; 0 (0)        ; 12288       ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated                                                                                                                                                                                                                                        ; work         ;
;    |generate_freq_word:U_GFQWD|                                                                         ; 135 (135)         ; 37 (37)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|generate_freq_word:U_GFQWD                                                                                                                                                                                                                                                                                                           ; work         ;
;    |powerup_reset:U_PURST|                                                                              ; 46 (46)           ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|powerup_reset:U_PURST                                                                                                                                                                                                                                                                                                                ; work         ;
;    |sld_hub:auto_hub|                                                                                   ; 123 (1)           ; 90 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                     ; work         ;
;       |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|                                                    ; 122 (83)          ; 90 (62)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst                                                                                                                                                                                                                                                                        ; work         ;
;          |sld_rom_sr:hub_info_reg|                                                                      ; 22 (22)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg                                                                                                                                                                                                                                                ; work         ;
;          |sld_shadow_jsm:shadow_jsm|                                                                    ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                                                              ; work         ;
;    |sld_signaltap:auto_signaltap_0|                                                                     ; 518 (1)           ; 897 (88)     ; 180224      ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                                       ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                           ; 517 (0)           ; 809 (0)      ; 180224      ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                                                                 ; work         ;
;          |sld_signaltap_implb:sld_signaltap_body|                                                       ; 517 (120)         ; 809 (260)    ; 180224      ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body                                                                                                                                                                                                                          ; work         ;
;             |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                            ; 27 (0)            ; 76 (76)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                           ; work         ;
;                |lpm_decode:wdecoder|                                                                    ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                       ; work         ;
;                   |decode_4uf:auto_generated|                                                           ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated                                                                                                             ; work         ;
;                |lpm_mux:mux|                                                                            ; 25 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                               ; work         ;
;                   |mux_krc:auto_generated|                                                              ; 25 (25)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_krc:auto_generated                                                                                                                        ; work         ;
;             |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 180224      ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                          ; work         ;
;                |altsyncram_nq14:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 180224      ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_nq14:auto_generated                                                                                                                                           ; work         ;
;             |lpm_shiftreg:segment_offset_config_deserialize|                                            ; 0 (0)             ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                           ; work         ;
;             |lpm_shiftreg:status_register|                                                              ; 17 (17)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                             ; work         ;
;             |serial_crc_16:\tdo_crc_gen:tdo_crc_calc|                                                   ; 4 (4)             ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc                                                                                                                                                                                  ; work         ;
;             |sld_buffer_manager:sld_buffer_manager_inst|                                                ; 92 (92)           ; 69 (69)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                               ; work         ;
;             |sld_ela_control:ela_control|                                                               ; 104 (1)           ; 236 (1)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                              ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                      ; work         ;
;                |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 88 (0)            ; 220 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                       ; work         ;
;                   |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 132 (132)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                            ; work         ;
;                   |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 88 (0)            ; 88 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                        ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1  ; work         ;
;                |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                          ; 15 (15)           ; 11 (1)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                ; work         ;
;                   |lpm_shiftreg:trigger_config_deserialize|                                             ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                        ; work         ;
;             |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 134 (10)          ; 118 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                         ; work         ;
;                |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 8 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                               ; work         ;
;                   |cntr_9fi:auto_generated|                                                             ; 8 (8)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated                                                       ; work         ;
;                |lpm_counter:read_pointer_counter|                                                       ; 12 (0)            ; 12 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                        ; work         ;
;                   |cntr_d8j:auto_generated|                                                             ; 12 (12)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated                                                                                ; work         ;
;                |lpm_counter:status_advance_pointer_counter|                                             ; 7 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                              ; work         ;
;                   |cntr_7fi:auto_generated|                                                             ; 7 (7)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated                                                                      ; work         ;
;                |lpm_counter:status_read_pointer_counter|                                                ; 3 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                 ; work         ;
;                   |cntr_p1j:auto_generated|                                                             ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_p1j:auto_generated                                                                         ; work         ;
;                |lpm_shiftreg:info_data_shift_out|                                                       ; 25 (25)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                        ; work         ;
;                |lpm_shiftreg:ram_data_shift_out|                                                        ; 44 (44)           ; 44 (44)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                         ; work         ;
;                |lpm_shiftreg:status_data_shift_out|                                                     ; 25 (25)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                      ; work         ;
;             |sld_rom_sr:crc_rom_sr|                                                                     ; 19 (19)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                    ; work         ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                          ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+----------------------------------------------------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                                                ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+----------------------------------------------------+
; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ALTSYNCRAM                                                                                              ; AUTO ; ROM              ; 1024         ; 12           ; --           ; --           ; 12288  ; db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_nq14:auto_generated|ALTSYNCRAM ; M9K  ; Simple Dual Port ; 4096         ; 44           ; 4096         ; 44           ; 180224 ; None                                               ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+----------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                           ; Reason for Removal                                                                                                                                                                                  ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; button_in_out:U_BUTRST|counterR[18]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[18]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[18]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[18]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[17]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[17]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[17]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[17]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[16]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[16]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[16]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[16]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[15]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[15]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[15]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[15]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[13]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[13]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[13]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[13]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[8]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[8]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[8]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[8]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[5]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[5]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[5]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[5]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[19]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[19]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[19]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[19]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[14]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[14]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[14]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[14]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[12]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[12]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[12]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[12]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[11]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[11]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[11]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[11]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[10]                                                                                                                                                     ; Merged with button_in_out:U_BUTDOWN|counterR[10]                                                                                                                                                    ;
; button_in_out:U_BUTUP|counterR[10]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[10]                                                                                                                                                    ;
; button_in_out:U_BUTRST|counterR[9]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[9]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[9]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[9]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[7]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[7]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[7]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[7]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[6]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[6]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[6]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[6]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[4]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[4]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[4]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[4]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[3]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[3]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[3]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[3]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[2]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[2]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[2]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[2]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[1]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[1]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[1]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[1]                                                                                                                                                     ;
; button_in_out:U_BUTRST|counterR[0]                                                                                                                                                      ; Merged with button_in_out:U_BUTDOWN|counterR[0]                                                                                                                                                     ;
; button_in_out:U_BUTUP|counterR[0]                                                                                                                                                       ; Merged with button_in_out:U_BUTDOWN|counterR[0]                                                                                                                                                     ;
; Total Number of Removed Registers = 40                                                                                                                                                  ;                                                                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|segment_shift_clk_ena                                                       ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed                                                 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[0]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[0]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[1]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[1]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[2]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[2]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[3]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[3]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[4]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[4]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[5]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[5]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[6]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[6]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[7]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[7]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[8]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[8]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[9]  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[9]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[10] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[10] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[11] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[11] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[0]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[0]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[1]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[1]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[2]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[2]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[3]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[3]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[4]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[4]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[5]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[5]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[6]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[6]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[7]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[7]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[8]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[8]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[9]                                                   ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[9]                                             ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[10]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[10]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[11]                                                  ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[11]                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13..15]                        ; Stuck at GND due to stuck port data_in                                                                                                                                                              ;
; Total Number of Removed Registers = 28                                                                                                                                                  ;                                                                                                                                                                                                     ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                        ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[15] ; Stuck at GND              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[14], ;
;                                                                                                                                                              ; due to stuck port data_in ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13]  ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1183  ;
; Number of registers using Synchronous Clear  ; 109   ;
; Number of registers using Synchronous Load   ; 66    ;
; Number of registers using Asynchronous Clear ; 485   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 540   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                             ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                              ; Fan out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; generate_freq_word:U_GFQWD|FQWD[0]                                                                                                                                             ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[11]                                                                                                                                            ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[12]                                                                                                                                            ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[13]                                                                                                                                            ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[15]                                                                                                                                            ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[17]                                                                                                                                            ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[18]                                                                                                                                            ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[19]                                                                                                                                            ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[20]                                                                                                                                            ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[24]                                                                                                                                            ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[26]                                                                                                                                            ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[4]                                                                                                                                             ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[6]                                                                                                                                             ; 6       ;
; generate_freq_word:U_GFQWD|FWEN                                                                                                                                                ; 32      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[12] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_out_mode_ff                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]  ; 1       ;
; Total number of inverted registers = 31                                                                                                                                        ;         ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                                                    ;
+----------------------------------------------------+-----------------------------------------------------+------+
; Register Name                                      ; Megafunction                                        ; Type ;
+----------------------------------------------------+-----------------------------------------------------+------+
; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|RD[0..11] ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|Ram0_rtl_0 ; RAM  ;
+----------------------------------------------------+-----------------------------------------------------+------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 5:1                ; 19 bits   ; 57 LEs        ; 38 LEs               ; 19 LEs                 ; Yes        ; |top_sin_wave|generate_freq_word:U_GFQWD|FQWD[28]                                                                                                                                 ;
; 5:1                ; 13 bits   ; 39 LEs        ; 26 LEs               ; 13 LEs                 ; Yes        ; |top_sin_wave|generate_freq_word:U_GFQWD|FQWD[11]                                                                                                                                 ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[15]                               ;
; 3:1                ; 13 bits   ; 26 LEs        ; 13 LEs               ; 13 LEs                 ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[7]                                ;
; 3:1                ; 13 bits   ; 26 LEs        ; 0 LEs                ; 26 LEs                 ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[5]         ;
; 4:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[14]                                     ;
; 4:1                ; 13 bits   ; 26 LEs        ; 13 LEs               ; 13 LEs                 ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[0]   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]                   ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3]                        ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; No         ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                  ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                     ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                               ;
; 6:1                ; 9 bits    ; 36 LEs        ; 9 LEs                ; 27 LEs                 ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                           ;
; 34:1               ; 4 bits    ; 88 LEs        ; 56 LEs               ; 32 LEs                 ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                    ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Source assignments for dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------+


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: powerup_reset:U_PURST ;
+----------------+---------+-----------------------------------------+
; Parameter Name ; Value   ; Type                                    ;
+----------------+---------+-----------------------------------------+
; CNTMAX         ; 4999999 ; Signed Integer                          ;
+----------------+---------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: button_in_out:U_BUTUP  ;
+----------------+----------------------------------+-----------------+
; Parameter Name ; Value                            ; Type            ;
+----------------+----------------------------------+-----------------+
; CNT_WL         ; 20                               ; Signed Integer  ;
; CNT_MAX        ; 01111010000100100000             ; Unsigned Binary ;
; CNT_MAX68      ; 00000000000001011011100011011000 ; Unsigned Binary ;
; CNT_MAX78      ; 00000000000001101010110011111100 ; Unsigned Binary ;
+----------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: button_in_out:U_BUTDOWN ;
+----------------+----------------------------------+------------------+
; Parameter Name ; Value                            ; Type             ;
+----------------+----------------------------------+------------------+
; CNT_WL         ; 20                               ; Signed Integer   ;
; CNT_MAX        ; 01111010000100100000             ; Unsigned Binary  ;
; CNT_MAX68      ; 00000000000001011011100011011000 ; Unsigned Binary  ;
; CNT_MAX78      ; 00000000000001101010110011111100 ; Unsigned Binary  ;
+----------------+----------------------------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: button_in_out:U_BUTRST ;
+----------------+----------------------------------+-----------------+
; Parameter Name ; Value                            ; Type            ;
+----------------+----------------------------------+-----------------+
; CNT_WL         ; 20                               ; Signed Integer  ;
; CNT_MAX        ; 01111010000100100000             ; Unsigned Binary ;
; CNT_MAX68      ; 00000000000001011011100011011000 ; Unsigned Binary ;
; CNT_MAX78      ; 00000000000001101010110011111100 ; Unsigned Binary ;
+----------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: generate_freq_word:U_GFQWD ;
+----------------+----------------------------------+---------------------+
; Parameter Name ; Value                            ; Type                ;
+----------------+----------------------------------+---------------------+
; VAL_FREQ_BASE  ; 00000101000111101011100001010001 ; Unsigned Binary     ;
; VAL_FREQ_MAX   ; 00110011001100110011001100101010 ; Unsigned Binary     ;
+----------------+----------------------------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds_core_sin:U_DDS ;
+----------------+-------+----------------------------------------+
; Parameter Name ; Value ; Type                                   ;
+----------------+-------+----------------------------------------+
; FW_WL          ; 32    ; Signed Integer                         ;
; RA_WL          ; 10    ; Signed Integer                         ;
; RD_WL          ; 12    ; Signed Integer                         ;
+----------------+-------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                                                                                                                   ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Parameter Name                                  ; Value                                                                                                                                                          ; Type           ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; lpm_type                                        ; sld_signaltap                                                                                                                                                  ; String         ;
; sld_node_info                                   ; 805334528                                                                                                                                                      ; Untyped        ;
; SLD_IP_VERSION                                  ; 6                                                                                                                                                              ; Signed Integer ;
; SLD_IP_MINOR_VERSION                            ; 0                                                                                                                                                              ; Signed Integer ;
; SLD_COMMON_IP_VERSION                           ; 0                                                                                                                                                              ; Signed Integer ;
; sld_data_bits                                   ; 44                                                                                                                                                             ; Untyped        ;
; sld_trigger_bits                                ; 44                                                                                                                                                             ; Untyped        ;
; SLD_NODE_CRC_BITS                               ; 32                                                                                                                                                             ; Signed Integer ;
; sld_node_crc_hiword                             ; 31924                                                                                                                                                          ; Untyped        ;
; sld_node_crc_loword                             ; 9439                                                                                                                                                           ; Untyped        ;
; SLD_INCREMENTAL_ROUTING                         ; 0                                                                                                                                                              ; Signed Integer ;
; sld_sample_depth                                ; 4096                                                                                                                                                           ; Untyped        ;
; sld_segment_size                                ; 4096                                                                                                                                                           ; Untyped        ;
; sld_ram_block_type                              ; M9K                                                                                                                                                            ; Untyped        ;
; sld_state_bits                                  ; 11                                                                                                                                                             ; Untyped        ;
; sld_buffer_full_stop                            ; 1                                                                                                                                                              ; Untyped        ;
; SLD_MEM_ADDRESS_BITS                            ; 7                                                                                                                                                              ; Signed Integer ;
; SLD_DATA_BIT_CNTR_BITS                          ; 4                                                                                                                                                              ; Signed Integer ;
; sld_trigger_level                               ; 1                                                                                                                                                              ; Untyped        ;
; sld_trigger_in_enabled                          ; 0                                                                                                                                                              ; Untyped        ;
; SLD_HPS_TRIGGER_IN_ENABLED                      ; 0                                                                                                                                                              ; Signed Integer ;
; SLD_HPS_TRIGGER_OUT_ENABLED                     ; 0                                                                                                                                                              ; Signed Integer ;
; SLD_HPS_EVENT_ENABLED                           ; 0                                                                                                                                                              ; Signed Integer ;
; SLD_HPS_EVENT_ID                                ; 0                                                                                                                                                              ; Signed Integer ;
; sld_advanced_trigger_entity                     ; basic,1,                                                                                                                                                       ; Untyped        ;
; sld_trigger_level_pipeline                      ; 1                                                                                                                                                              ; Untyped        ;
; sld_enable_advanced_trigger                     ; 0                                                                                                                                                              ; Untyped        ;
; SLD_ADVANCED_TRIGGER_1                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_2                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_3                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_4                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_5                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_6                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_7                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_8                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_9                          ; NONE                                                                                                                                                           ; String         ;
; SLD_ADVANCED_TRIGGER_10                         ; NONE                                                                                                                                                           ; String         ;
; sld_inversion_mask_length                       ; 158                                                                                                                                                            ; Untyped        ;
; sld_inversion_mask                              ; 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger                            ; 0                                                                                                                                                              ; Untyped        ;
; SLD_STATE_FLOW_MGR_ENTITY                       ; state_flow_mgr_entity.vhd                                                                                                                                      ; String         ;
; sld_state_flow_use_generated                    ; 0                                                                                                                                                              ; Untyped        ;
; sld_current_resource_width                      ; 1                                                                                                                                                              ; Untyped        ;
; sld_attribute_mem_mode                          ; OFF                                                                                                                                                            ; Untyped        ;
; SLD_STORAGE_QUALIFIER_BITS                      ; 1                                                                                                                                                              ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_GAP_RECORD                ; 0                                                                                                                                                              ; Signed Integer ;
; SLD_STORAGE_QUALIFIER_MODE                      ; OFF                                                                                                                                                            ; String         ;
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0                                                                                                                                                              ; Signed Integer ;
; sld_storage_qualifier_inversion_mask_length     ; 0                                                                                                                                                              ; Untyped        ;
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic                                                                                                                                                          ; String         ;
; SLD_STORAGE_QUALIFIER_PIPELINE                  ; 0                                                                                                                                                              ; Signed Integer ;
+-------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0 ;
+------------------------------------+----------------------------------------------------+-----------------------+
; Parameter Name                     ; Value                                              ; Type                  ;
+------------------------------------+----------------------------------------------------+-----------------------+
; BYTE_SIZE_BLOCK                    ; 8                                                  ; Untyped               ;
; AUTO_CARRY_CHAINS                  ; ON                                                 ; AUTO_CARRY            ;
; IGNORE_CARRY_BUFFERS               ; OFF                                                ; IGNORE_CARRY          ;
; AUTO_CASCADE_CHAINS                ; ON                                                 ; AUTO_CASCADE          ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                                ; IGNORE_CASCADE        ;
; WIDTH_BYTEENA                      ; 1                                                  ; Untyped               ;
; OPERATION_MODE                     ; ROM                                                ; Untyped               ;
; WIDTH_A                            ; 12                                                 ; Untyped               ;
; WIDTHAD_A                          ; 10                                                 ; Untyped               ;
; NUMWORDS_A                         ; 1024                                               ; Untyped               ;
; OUTDATA_REG_A                      ; UNREGISTERED                                       ; Untyped               ;
; ADDRESS_ACLR_A                     ; NONE                                               ; Untyped               ;
; OUTDATA_ACLR_A                     ; NONE                                               ; Untyped               ;
; WRCONTROL_ACLR_A                   ; NONE                                               ; Untyped               ;
; INDATA_ACLR_A                      ; NONE                                               ; Untyped               ;
; BYTEENA_ACLR_A                     ; NONE                                               ; Untyped               ;
; WIDTH_B                            ; 1                                                  ; Untyped               ;
; WIDTHAD_B                          ; 1                                                  ; Untyped               ;
; NUMWORDS_B                         ; 1                                                  ; Untyped               ;
; INDATA_REG_B                       ; CLOCK1                                             ; Untyped               ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                             ; Untyped               ;
; RDCONTROL_REG_B                    ; CLOCK1                                             ; Untyped               ;
; ADDRESS_REG_B                      ; CLOCK1                                             ; Untyped               ;
; OUTDATA_REG_B                      ; UNREGISTERED                                       ; Untyped               ;
; BYTEENA_REG_B                      ; CLOCK1                                             ; Untyped               ;
; INDATA_ACLR_B                      ; NONE                                               ; Untyped               ;
; WRCONTROL_ACLR_B                   ; NONE                                               ; Untyped               ;
; ADDRESS_ACLR_B                     ; NONE                                               ; Untyped               ;
; OUTDATA_ACLR_B                     ; NONE                                               ; Untyped               ;
; RDCONTROL_ACLR_B                   ; NONE                                               ; Untyped               ;
; BYTEENA_ACLR_B                     ; NONE                                               ; Untyped               ;
; WIDTH_BYTEENA_A                    ; 1                                                  ; Untyped               ;
; WIDTH_BYTEENA_B                    ; 1                                                  ; Untyped               ;
; RAM_BLOCK_TYPE                     ; AUTO                                               ; Untyped               ;
; BYTE_SIZE                          ; 8                                                  ; Untyped               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                          ; Untyped               ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                               ; Untyped               ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                               ; Untyped               ;
; INIT_FILE                          ; db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif ; Untyped               ;
; INIT_FILE_LAYOUT                   ; PORT_A                                             ; Untyped               ;
; MAXIMUM_DEPTH                      ; 0                                                  ; Untyped               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                                             ; Untyped               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                             ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                                             ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                             ; Untyped               ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                                    ; Untyped               ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                                    ; Untyped               ;
; ENABLE_ECC                         ; FALSE                                              ; Untyped               ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                                              ; Untyped               ;
; WIDTH_ECCSTATUS                    ; 3                                                  ; Untyped               ;
; DEVICE_FAMILY                      ; Cyclone III                                        ; Untyped               ;
; CBXI_PARAMETER                     ; altsyncram_k581                                    ; Untyped               ;
+------------------------------------+----------------------------------------------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                           ;
+-------------------------------------------+----------------------------------------------------------------+
; Name                                      ; Value                                                          ;
+-------------------------------------------+----------------------------------------------------------------+
; Number of entity instances                ; 1                                                              ;
; Entity Instance                           ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                            ;
;     -- WIDTH_A                            ; 12                                                             ;
;     -- NUMWORDS_A                         ; 1024                                                           ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                   ;
;     -- WIDTH_B                            ; 1                                                              ;
;     -- NUMWORDS_B                         ; 1                                                              ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                         ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                   ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                           ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                      ;
+-------------------------------------------+----------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                                    ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Storage Qualifier Type ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
; 0              ; auto_signaltap_0 ; 44                  ; 44               ; 4096         ; 1        ; continuous             ; sequential           ; 1                  ; 0                           ; no              ; no               ; no                       ;
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+


+-----------------------------------------------+
; Elapsed Time Per Partition                    ;
+--------------------------------+--------------+
; Partition Name                 ; Elapsed Time ;
+--------------------------------+--------------+
; sld_signaltap:auto_signaltap_0 ; 00:00:01     ;
; Top                            ; 00:00:00     ;
; sld_hub:auto_hub               ; 00:00:00     ;
+--------------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "auto_signaltap_0"                                                                                                 ;
+-------------------------------------+---------------+-----------+----------------+-------------------+-----------------------------------------------+---------+
; Name                                ; Type          ; Status    ; Partition Name ; Netlist Type Used ; Actual Connection                             ; Details ;
+-------------------------------------+---------------+-----------+----------------+-------------------+-----------------------------------------------+---------+
; CLK                                 ; pre-synthesis ; connected ; Top            ; post-synthesis    ; CLK                                           ; N/A     ;
; SINOUT[0]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[0]                ; N/A     ;
; SINOUT[0]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[0]                ; N/A     ;
; SINOUT[10]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[10]               ; N/A     ;
; SINOUT[10]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[10]               ; N/A     ;
; SINOUT[11]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[11]               ; N/A     ;
; SINOUT[11]                          ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[11]               ; N/A     ;
; SINOUT[1]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[1]                ; N/A     ;
; SINOUT[1]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[1]                ; N/A     ;
; SINOUT[2]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[2]                ; N/A     ;
; SINOUT[2]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[2]                ; N/A     ;
; SINOUT[3]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[3]                ; N/A     ;
; SINOUT[3]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[3]                ; N/A     ;
; SINOUT[4]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[4]                ; N/A     ;
; SINOUT[4]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[4]                ; N/A     ;
; SINOUT[5]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[5]                ; N/A     ;
; SINOUT[5]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[5]                ; N/A     ;
; SINOUT[6]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[6]                ; N/A     ;
; SINOUT[6]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[6]                ; N/A     ;
; SINOUT[7]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[7]                ; N/A     ;
; SINOUT[7]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[7]                ; N/A     ;
; SINOUT[8]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[8]                ; N/A     ;
; SINOUT[8]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[8]                ; N/A     ;
; SINOUT[9]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[9]                ; N/A     ;
; SINOUT[9]                           ; pre-synthesis ; connected ; Top            ; post-synthesis    ; dds_core_sin:U_DDS|sinout_R[9]                ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[0]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[0]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[0]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[0]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[10] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[10]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[10] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[10]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[11] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[11]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[11] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[11]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[12] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[12]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[12] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[12]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[13] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[13]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[13] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[13]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[14] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[14]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[14] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[14]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[15] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[15]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[15] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[15]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[16] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[16]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[16] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[16]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[17] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[17]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[17] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[17]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[18] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[18]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[18] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[18]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[19] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[19]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[19] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[19]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[1]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[1]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[1]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[1]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[20] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[20]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[20] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[20]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[21] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[21]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[21] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[21]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[22] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[22]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[22] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[22]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[23] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[23]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[23] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[23]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[24] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[24]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[24] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[24]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[25] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[25]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[25] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[25]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[26] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[26]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[26] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[26]~_wirecell ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[27] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[27]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[27] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[27]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[28] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[28]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[28] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[28]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[29] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[29]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[29] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[29]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[2]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[2]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[2]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[2]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[30] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[30]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[30] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[30]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[31] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[31]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[31] ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[31]           ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[3]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[3]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[3]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[3]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[4]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[4]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[4]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[4]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[5]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[5]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[5]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[5]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[6]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[6]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[6]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[6]~_wirecell  ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[7]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[7]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[7]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[7]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[8]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[8]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[8]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[8]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[9]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[9]            ; N/A     ;
; generate_freq_word:U_GFQWD|FQWD[9]  ; pre-synthesis ; connected ; Top            ; post-synthesis    ; generate_freq_word:U_GFQWD|FQWD[9]            ; N/A     ;
+-------------------------------------+---------------+-----------+----------------+-------------------+-----------------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Sun Jun 07 20:49:06 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_sin_wave -c top_sin_wave
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/powerup_reset.v
    Info (12023): Found entity 1: powerup_reset
Info (12021): Found 2 design units, including 2 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/top_sin_wave.v
    Info (12023): Found entity 1: top_sin_wave
    Info (12023): Found entity 2: generate_freq_word
Info (12021): Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/button.v
    Info (12023): Found entity 1: button_in_out
Info (12021): Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core.v
    Info (12023): Found entity 1: dds_core_sin
Info (12021): Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core_rom.v
    Info (12023): Found entity 1: DDS_CORE_ROM
Warning (10236): Verilog HDL Implicit Net warning at top_sin_wave.v(65): created implicit net for "pu_rst_W"
Info (12127): Elaborating entity "top_sin_wave" for the top level hierarchy
Info (12128): Elaborating entity "powerup_reset" for hierarchy "powerup_reset:U_PURST"
Info (12128): Elaborating entity "button_in_out" for hierarchy "button_in_out:U_BUTUP"
Info (12128): Elaborating entity "generate_freq_word" for hierarchy "generate_freq_word:U_GFQWD"
Info (12128): Elaborating entity "dds_core_sin" for hierarchy "dds_core_sin:U_DDS"
Info (12128): Elaborating entity "DDS_CORE_ROM" for hierarchy "dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nq14.tdf
    Info (12023): Found entity 1: altsyncram_nq14
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_krc.tdf
    Info (12023): Found entity 1: mux_krc
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_4uf.tdf
    Info (12023): Found entity 1: decode_4uf
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_9fi.tdf
    Info (12023): Found entity 1: cntr_9fi
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_jfc.tdf
    Info (12023): Found entity 1: cmpr_jfc
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_d8j.tdf
    Info (12023): Found entity 1: cntr_d8j
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_7fi.tdf
    Info (12023): Found entity 1: cntr_7fi
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ifc.tdf
    Info (12023): Found entity 1: cmpr_ifc
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_p1j.tdf
    Info (12023): Found entity 1: cntr_p1j
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_efc.tdf
    Info (12023): Found entity 1: cmpr_efc
Info (12033): Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|Ram0_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 12
        Info (286033): Parameter WIDTHAD_A set to 10
        Info (286033): Parameter NUMWORDS_A set to 1024
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter INIT_FILE set to db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif
Info (12130): Elaborated megafunction instantiation "dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0"
Info (12133): Instantiated megafunction "dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "12"
    Info (12134): Parameter "WIDTHAD_A" = "10"
    Info (12134): Parameter "NUMWORDS_A" = "1024"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "INIT_FILE" = "db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_k581.tdf
    Info (12023): Found entity 1: altsyncram_k581
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (18057): The assignment to disallow NOT gate push-back on register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_out_mode_ff" is ignored
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "sld_hub:auto_hub|receive[0][0]" is stuck at GND
Info (35024): Succesfully connected in-system debug instance "auto_signaltap_0" to all 89 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 1683 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 7 input pins
    Info (21059): Implemented 14 output pins
    Info (21061): Implemented 1605 logic cells
    Info (21064): Implemented 56 RAM segments
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 551 megabytes
    Info: Processing ended: Sun Jun 07 20:49:14 2015
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:07


