Assembler report for top_sin_wave
Sun Jun 07 20:49:30 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Assembler Summary
  3. Assembler Settings
  4. Assembler Encrypted IP Cores Summary
  5. Assembler Generated Files
  6. Assembler Device Options: D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.sof
  7. Assembler Device Options: D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.pof
  8. Assembler Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Sun Jun 07 20:49:30 2015 ;
; Revision Name         ; top_sin_wave                          ;
; Top-level Entity Name ; top_sin_wave                          ;
; Family                ; Cyclone III                           ;
; Device                ; EP3C16F484C6                          ;
+-----------------------+---------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Assembler Settings                                                                                     ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option                                                                      ; Setting  ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use configuration device                                                    ; On       ; Off           ;
; Use smart compilation                                                       ; Off      ; Off           ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
; Enable compact report table                                                 ; Off      ; Off           ;
; Generate compressed bitstreams                                              ; On       ; On            ;
; Compression mode                                                            ; Off      ; Off           ;
; Clock source for configuration device                                       ; Internal ; Internal      ;
; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
; Divide clock frequency by                                                   ; 1        ; 1             ;
; Auto user code                                                              ; On       ; On            ;
; Configuration device                                                        ; Auto     ; Auto          ;
; Configuration device auto user code                                         ; Off      ; Off           ;
; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
; Hexadecimal Output File start address                                       ; 0        ; 0             ;
; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
; Release clears before tri-states                                            ; Off      ; Off           ;
; Auto-restart configuration after error                                      ; On       ; On            ;
; Enable OCT_DONE                                                             ; Off      ; Off           ;
; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
+-----------------------------------------------------------------------------+----------+---------------+


+------------------------------------------------+
; Assembler Encrypted IP Cores Summary           ;
+--------+------------------------+--------------+
; Vendor ; IP Core Name           ; License Type ;
+--------+------------------------+--------------+
; Altera ; Signal Tap (6AF7 BCE1) ; Licensed     ;
; Altera ; Signal Tap (6AF7 BCEC) ; Licensed     ;
+--------+------------------------+--------------+


+--------------------------------------------------------------------------+
; Assembler Generated Files                                                ;
+--------------------------------------------------------------------------+
; File Name                                                                ;
+--------------------------------------------------------------------------+
; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.sof ;
; D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.pof ;
+--------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.sof ;
+----------------+-----------------------------------------------------------------------------------+
; Option         ; Setting                                                                           ;
+----------------+-----------------------------------------------------------------------------------+
; Device         ; EP3C16F484C6                                                                      ;
; JTAG usercode  ; 0x001C7E21                                                                        ;
; Checksum       ; 0x001C7E21                                                                        ;
+----------------+-----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.pof ;
+--------------------+-------------------------------------------------------------------------------+
; Option             ; Setting                                                                       ;
+--------------------+-------------------------------------------------------------------------------+
; Device             ; EPCS4                                                                         ;
; JTAG usercode      ; 0x00000000                                                                    ;
; Checksum           ; 0x05B7E8CE                                                                    ;
; Compression Ratio  ; 3                                                                             ;
+--------------------+-------------------------------------------------------------------------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Sun Jun 07 20:49:28 2015
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top_sin_wave -c top_sin_wave
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 450 megabytes
    Info: Processing ended: Sun Jun 07 20:49:30 2015
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


