Fitter report for top_sin_wave
Sun Jun 07 20:49:26 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Fitter Netlist Optimizations
  7. Incremental Compilation Preservation Summary
  8. Incremental Compilation Partition Settings
  9. Incremental Compilation Placement Preservation
 10. Pin-Out File
 11. Fitter Resource Usage Summary
 12. Fitter Partition Statistics
 13. Input Pins
 14. Output Pins
 15. Dual Purpose and Dedicated Pins
 16. I/O Bank Usage
 17. All Package Pins
 18. Fitter Resource Utilization by Entity
 19. Delay Chain Summary
 20. Pad To Core Delay Chain Fanout
 21. Control Signals
 22. Global & Other Fast Signals
 23. Non-Global High Fan-Out Signals
 24. Fitter RAM Summary
 25. |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ALTSYNCRAM
 26. Routing Usage Summary
 27. LAB Logic Elements
 28. LAB-wide Signals
 29. LAB Signals Sourced
 30. LAB Signals Sourced Out
 31. LAB Distinct Inputs
 32. I/O Rules Summary
 33. I/O Rules Details
 34. I/O Rules Matrix
 35. Fitter Device Options
 36. Operating Settings and Conditions
 37. Fitter Messages
 38. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Sun Jun 07 20:49:26 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; top_sin_wave                                ;
; Top-level Entity Name              ; top_sin_wave                                ;
; Family                             ; Cyclone III                                 ;
; Device                             ; EP3C16F484C6                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 1,507 / 15,408 ( 10 % )                     ;
;     Total combinational functions  ; 921 / 15,408 ( 6 % )                        ;
;     Dedicated logic registers      ; 1,171 / 15,408 ( 8 % )                      ;
; Total registers                    ; 1171                                        ;
; Total pins                         ; 17 / 347 ( 5 % )                            ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 192,512 / 516,096 ( 37 % )                  ;
; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
; Total PLLs                         ; 0 / 4 ( 0 % )                               ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; EP3C16F484C6                          ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Use smart compilation                                                      ; Off                                   ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths        ; IO Paths and Minimum TPD Paths        ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
; Enable Beneficial Skew Optimization                                        ; Off                                   ; Off                                   ;
; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.33        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;  11.1%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------+
; I/O Assignment Warnings                    ;
+------------+-------------------------------+
; Pin Name   ; Reason                        ;
+------------+-------------------------------+
; CLKOUT     ; Incomplete set of assignments ;
; SINOUT[0]  ; Incomplete set of assignments ;
; SINOUT[1]  ; Incomplete set of assignments ;
; SINOUT[2]  ; Incomplete set of assignments ;
; SINOUT[3]  ; Incomplete set of assignments ;
; SINOUT[4]  ; Incomplete set of assignments ;
; SINOUT[5]  ; Incomplete set of assignments ;
; SINOUT[6]  ; Incomplete set of assignments ;
; SINOUT[7]  ; Incomplete set of assignments ;
; SINOUT[8]  ; Incomplete set of assignments ;
; SINOUT[9]  ; Incomplete set of assignments ;
; SINOUT[10] ; Incomplete set of assignments ;
; SINOUT[11] ; Incomplete set of assignments ;
; CLK        ; Incomplete set of assignments ;
; BUTRST     ; Incomplete set of assignments ;
; BUTUP      ; Incomplete set of assignments ;
; BUTDOWN    ; Incomplete set of assignments ;
+------------+-------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                     ;
+---------------------------------+-----------------+------------------+---------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node                            ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node                                                                                            ; Destination Port ; Destination Port Name ;
+---------------------------------+-----------------+------------------+---------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; dds_core_sin:U_DDS|sinout_R[0]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a0  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[1]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a1  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[2]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a2  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[3]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a3  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[4]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a4  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[5]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a5  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[6]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a6  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[7]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a7  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[8]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a8  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[9]  ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a9  ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[10] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a10 ; PORTADATAOUT     ;                       ;
; dds_core_sin:U_DDS|sinout_R[11] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ram_block1a11 ; PORTADATAOUT     ;                       ;
+---------------------------------+-----------------+------------------+---------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------+------------------+-----------------------+


+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                      ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 2216 ) ; 0.00 % ( 0 / 2216 )        ; 0.00 % ( 0 / 2216 )      ;
;     -- Achieved     ; 0.00 % ( 0 / 2216 ) ; 0.00 % ( 0 / 2216 )        ; 0.00 % ( 0 / 2216 )      ;
;                     ;                     ;                            ;                          ;
; Routing (by net)    ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+---------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_hub:auto_hub               ;
; sld_signaltap:auto_signaltap_0 ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_signaltap:auto_signaltap_0 ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 533 )    ; N/A                     ; Source File       ; N/A                 ;       ;
; sld_hub:auto_hub               ; 0.00 % ( 0 / 213 )    ; N/A                     ; Post-Synthesis    ; N/A                 ;       ;
; sld_signaltap:auto_signaltap_0 ; 0.00 % ( 0 / 1460 )   ; N/A                     ; Post-Synthesis    ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.pin.


+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                            ;
+---------------------------------------------+----------------------------+
; Resource                                    ; Usage                      ;
+---------------------------------------------+----------------------------+
; Total logic elements                        ; 1,507 / 15,408 ( 10 % )    ;
;     -- Combinational with no register       ; 336                        ;
;     -- Register only                        ; 586                        ;
;     -- Combinational with a register        ; 585                        ;
;                                             ;                            ;
; Logic element usage by number of LUT inputs ;                            ;
;     -- 4 input functions                    ; 360                        ;
;     -- 3 input functions                    ; 215                        ;
;     -- <=2 input functions                  ; 346                        ;
;     -- Register only                        ; 586                        ;
;                                             ;                            ;
; Logic elements by mode                      ;                            ;
;     -- normal mode                          ; 682                        ;
;     -- arithmetic mode                      ; 239                        ;
;                                             ;                            ;
; Total registers*                            ; 1,171 / 17,068 ( 7 % )     ;
;     -- Dedicated logic registers            ; 1,171 / 15,408 ( 8 % )     ;
;     -- I/O registers                        ; 0 / 1,660 ( 0 % )          ;
;                                             ;                            ;
; Total LABs:  partially or completely used   ; 119 / 963 ( 12 % )         ;
; Virtual pins                                ; 0                          ;
; I/O pins                                    ; 17 / 347 ( 5 % )           ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )             ;
;     -- Dedicated input pins                 ; 3 / 9 ( 33 % )             ;
;                                             ;                            ;
; Global signals                              ; 4                          ;
; M9Ks                                        ; 24 / 56 ( 43 % )           ;
; Total block memory bits                     ; 192,512 / 516,096 ( 37 % ) ;
; Total block memory implementation bits      ; 221,184 / 516,096 ( 43 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )            ;
; PLLs                                        ; 0 / 4 ( 0 % )              ;
; Global clocks                               ; 4 / 20 ( 20 % )            ;
; JTAGs                                       ; 1 / 1 ( 100 % )            ;
; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
; Average interconnect usage (total/H/V)      ; 2% / 2% / 2%               ;
; Peak interconnect usage (total/H/V)         ; 9% / 7% / 13%              ;
; Maximum fan-out                             ; 715                        ;
; Highest non-global fan-out                  ; 158                        ;
; Total fan-out                               ; 7448                       ;
; Average fan-out                             ; 2.87                       ;
+---------------------------------------------+----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                                                 ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+--------------------------------+
; Statistic                                   ; Top                 ; sld_hub:auto_hub      ; sld_signaltap:auto_signaltap_0 ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                   ; Low                            ; Low                            ;
;                                             ;                     ;                       ;                                ;                                ;
; Total logic elements                        ; 321 / 15408 ( 2 % ) ; 146 / 15408 ( < 1 % ) ; 1040 / 15408 ( 7 % )           ; 0 / 15408 ( 0 % )              ;
;     -- Combinational with no register       ; 137                 ; 56                    ; 143                            ; 0                              ;
;     -- Register only                        ; 43                  ; 23                    ; 520                            ; 0                              ;
;     -- Combinational with a register        ; 141                 ; 67                    ; 377                            ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                       ;                                ;                                ;
;     -- 4 input functions                    ; 80                  ; 45                    ; 235                            ; 0                              ;
;     -- 3 input functions                    ; 38                  ; 37                    ; 140                            ; 0                              ;
;     -- <=2 input functions                  ; 160                 ; 41                    ; 145                            ; 0                              ;
;     -- Register only                        ; 43                  ; 23                    ; 520                            ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Logic elements by mode                      ;                     ;                       ;                                ;                                ;
;     -- normal mode                          ; 135                 ; 115                   ; 432                            ; 0                              ;
;     -- arithmetic mode                      ; 143                 ; 8                     ; 88                             ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Total registers                             ; 184                 ; 90                    ; 897                            ; 0                              ;
;     -- Dedicated logic registers            ; 184 / 15408 ( 1 % ) ; 90 / 15408 ( < 1 % )  ; 897 / 15408 ( 6 % )            ; 0 / 15408 ( 0 % )              ;
;     -- I/O registers                        ; 0                   ; 0                     ; 0                              ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Total LABs:  partially or completely used   ; 28 / 963 ( 3 % )    ; 13 / 963 ( 1 % )      ; 85 / 963 ( 9 % )               ; 0 / 963 ( 0 % )                ;
;                                             ;                     ;                       ;                                ;                                ;
; Virtual pins                                ; 0                   ; 0                     ; 0                              ; 0                              ;
; I/O pins                                    ; 17                  ; 0                     ; 0                              ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ; 0 / 112 ( 0 % )                ;
; Total memory bits                           ; 12288               ; 0                     ; 180224                         ; 0                              ;
; Total RAM block bits                        ; 18432               ; 0                     ; 202752                         ; 0                              ;
; JTAG                                        ; 1 / 1 ( 100 % )     ; 0 / 1 ( 0 % )         ; 0 / 1 ( 0 % )                  ; 0 / 1 ( 0 % )                  ;
; M9K                                         ; 2 / 56 ( 3 % )      ; 0 / 56 ( 0 % )        ; 22 / 56 ( 39 % )               ; 0 / 56 ( 0 % )                 ;
; Clock control block                         ; 3 / 24 ( 12 % )     ; 0 / 24 ( 0 % )        ; 1 / 24 ( 4 % )                 ; 0 / 24 ( 0 % )                 ;
;                                             ;                     ;                       ;                                ;                                ;
; Connections                                 ;                     ;                       ;                                ;                                ;
;     -- Input Connections                    ; 1                   ; 133                   ; 1207                           ; 0                              ;
;     -- Registered Input Connections         ; 0                   ; 99                    ; 956                            ; 0                              ;
;     -- Output Connections                   ; 1157                ; 183                   ; 1                              ; 0                              ;
;     -- Registered Output Connections        ; 62                  ; 182                   ; 0                              ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Internal Connections                        ;                     ;                       ;                                ;                                ;
;     -- Total Connections                    ; 2612                ; 863                   ; 5322                           ; 5                              ;
;     -- Registered Connections               ; 583                 ; 615                   ; 2963                           ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; External Connections                        ;                     ;                       ;                                ;                                ;
;     -- Top                                  ; 0                   ; 123                   ; 1035                           ; 0                              ;
;     -- sld_hub:auto_hub                     ; 123                 ; 20                    ; 173                            ; 0                              ;
;     -- sld_signaltap:auto_signaltap_0       ; 1035                ; 173                   ; 0                              ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 0                   ; 0                     ; 0                              ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Partition Interface                         ;                     ;                       ;                                ;                                ;
;     -- Input Ports                          ; 7                   ; 21                    ; 147                            ; 0                              ;
;     -- Output Ports                         ; 46                  ; 39                    ; 100                            ; 0                              ;
;     -- Bidir Ports                          ; 0                   ; 0                     ; 0                              ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Registered Ports                            ;                     ;                       ;                                ;                                ;
;     -- Registered Input Ports               ; 0                   ; 4                     ; 36                             ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 28                    ; 89                             ; 0                              ;
;                                             ;                     ;                       ;                                ;                                ;
; Port Connectivity                           ;                     ;                       ;                                ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 1                     ; 0                              ; 0                              ;
;     -- Output Ports driven by GND           ; 0                   ; 1                     ; 0                              ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                     ; 0                              ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                     ; 0                              ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 1                     ; 35                             ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                     ; 0                              ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 2                     ; 40                             ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 15                    ; 89                             ; 0                              ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                   ;
+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; BUTDOWN ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; BUTRST  ; H2    ; 1        ; 0            ; 21           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; BUTUP   ; G3    ; 1        ; 0            ; 23           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; CLK     ; G21   ; 6        ; 41           ; 15           ; 0            ; 716                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; CLKOUT     ; M21   ; 5        ; 41           ; 14           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[0]  ; E9    ; 8        ; 11           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[10] ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[11] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[1]  ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[2]  ; A8    ; 8        ; 14           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[3]  ; A10   ; 8        ; 16           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[4]  ; E13   ; 7        ; 23           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[5]  ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[6]  ; H11   ; 8        ; 19           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[7]  ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[8]  ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
; SINOUT[9]  ; B10   ; 8        ; 16           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                                    ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; Location ; Pin Name                               ; Reserved As              ; User Signal Name        ; Pin Type                  ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
; D1       ; DIFFIO_L4n, DATA1, ASDO                ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO            ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
; K6       ; nSTATUS                                ; -                        ; -                       ; Dedicated Programming Pin ;
; K2       ; DCLK                                   ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
; K1       ; DATA0                                  ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
; K5       ; nCONFIG                                ; -                        ; -                       ; Dedicated Programming Pin ;
; L5       ; TDI                                    ; -                        ; altera_reserved_tdi     ; JTAG Pin                  ;
; L2       ; TCK                                    ; -                        ; altera_reserved_tck     ; JTAG Pin                  ;
; L1       ; TMS                                    ; -                        ; altera_reserved_tms     ; JTAG Pin                  ;
; L4       ; TDO                                    ; -                        ; altera_reserved_tdo     ; JTAG Pin                  ;
; L3       ; nCE                                    ; -                        ; -                       ; Dedicated Programming Pin ;
; M18      ; CONF_DONE                              ; -                        ; -                       ; Dedicated Programming Pin ;
; M17      ; MSEL0                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; L18      ; MSEL1                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; L17      ; MSEL2                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; K20      ; MSEL3                                  ; -                        ; -                       ; Dedicated Programming Pin ;
; K22      ; DIFFIO_R16n, nCEO                      ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
; C13      ; DIFFIO_T19n, PADD7                     ; Use as regular IO        ; SINOUT[1]               ; Dual Purpose Pin          ;
; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO        ; SINOUT[10]              ; Dual Purpose Pin          ;
; B10      ; DIFFIO_T14p, PADD15                    ; Use as regular IO        ; SINOUT[9]               ; Dual Purpose Pin          ;
; A8       ; DIFFIO_T12n, DATA2                     ; Use as regular IO        ; SINOUT[2]               ; Dual Purpose Pin          ;
; B8       ; DIFFIO_T12p, DATA3                     ; Use as regular IO        ; SINOUT[7]               ; Dual Purpose Pin          ;
; A6       ; DIFFIO_T10n, PADD19                    ; Use as regular IO        ; SINOUT[8]               ; Dual Purpose Pin          ;
; B6       ; DIFFIO_T10p, DATA15                    ; Use as regular IO        ; SINOUT[5]               ; Dual Purpose Pin          ;
+----------+----------------------------------------+--------------------------+-------------------------+---------------------------+


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 8 / 33 ( 24 % ) ; 2.5V          ; --           ;
; 2        ; 0 / 48 ( 0 % )  ; 2.5V          ; --           ;
; 3        ; 0 / 46 ( 0 % )  ; 2.5V          ; --           ;
; 4        ; 0 / 41 ( 0 % )  ; 2.5V          ; --           ;
; 5        ; 1 / 46 ( 2 % )  ; 2.5V          ; --           ;
; 6        ; 2 / 43 ( 5 % )  ; 2.5V          ; --           ;
; 7        ; 3 / 47 ( 6 % )  ; 2.5V          ; --           ;
; 8        ; 8 / 43 ( 19 % ) ; 2.5V          ; --           ;
+----------+-----------------+---------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                                        ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A6       ; 336        ; 8        ; SINOUT[8]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A8       ; 332        ; 8        ; SINOUT[2]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A10      ; 326        ; 8        ; SINOUT[3]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B6       ; 337        ; 8        ; SINOUT[5]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B8       ; 333        ; 8        ; SINOUT[7]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B10      ; 327        ; 8        ; SINOUT[9]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; B13      ; 315        ; 7        ; SINOUT[10]                                                ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C13      ; 309        ; 7        ; SINOUT[1]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; E9       ; 338        ; 8        ; SINOUT[0]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E13      ; 311        ; 7        ; SINOUT[4]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F1       ; 16         ; 1        ; BUTDOWN                                                   ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; G3       ; 18         ; 1        ; BUTUP                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G21      ; 226        ; 6        ; CLK                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H2       ; 25         ; 1        ; BUTRST                                                    ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H11      ; 323        ; 8        ; SINOUT[6]                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J1       ; 29         ; 1        ; SINOUT[11]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
; L1       ; 35         ; 1        ; altera_reserved_tms                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L2       ; 34         ; 1        ; altera_reserved_tck                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L4       ; 36         ; 1        ; altera_reserved_tdo                                       ; output ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L5       ; 33         ; 1        ; altera_reserved_tdi                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M21      ; 219        ; 5        ; CLKOUT                                                    ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                              ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                                                                                                                                                                                ; Library Name ;
+---------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |top_sin_wave                                                                                           ; 1507 (2)    ; 1171 (0)                  ; 0 (0)         ; 192512      ; 24   ; 0            ; 0       ; 0         ; 17   ; 0            ; 336 (2)      ; 586 (0)           ; 585 (0)          ; |top_sin_wave                                                                                                                                                                                                                                                                                                                                      ; work         ;
;    |button_in_out:U_BUTDOWN|                                                                            ; 33 (33)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 4 (4)             ; 23 (23)          ; |top_sin_wave|button_in_out:U_BUTDOWN                                                                                                                                                                                                                                                                                                              ; work         ;
;    |button_in_out:U_BUTRST|                                                                             ; 22 (22)     ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 4 (4)             ; 3 (3)            ; |top_sin_wave|button_in_out:U_BUTRST                                                                                                                                                                                                                                                                                                               ; work         ;
;    |button_in_out:U_BUTUP|                                                                              ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 3 (3)            ; |top_sin_wave|button_in_out:U_BUTUP                                                                                                                                                                                                                                                                                                                ; work         ;
;    |dds_core_sin:U_DDS|                                                                                 ; 74 (74)     ; 74 (74)                   ; 0 (0)         ; 12288       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 29 (29)           ; 45 (45)          ; |top_sin_wave|dds_core_sin:U_DDS                                                                                                                                                                                                                                                                                                                   ; work         ;
;       |DDS_CORE_ROM:u_sinrom|                                                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 12288       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom                                                                                                                                                                                                                                                                                             ; work         ;
;          |altsyncram:Ram0_rtl_0|                                                                        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 12288       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0                                                                                                                                                                                                                                                                       ; work         ;
;             |altsyncram_k581:auto_generated|                                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 12288       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated                                                                                                                                                                                                                                        ; work         ;
;    |generate_freq_word:U_GFQWD|                                                                         ; 137 (137)   ; 37 (37)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 100 (100)    ; 2 (2)             ; 35 (35)          ; |top_sin_wave|generate_freq_word:U_GFQWD                                                                                                                                                                                                                                                                                                           ; work         ;
;    |powerup_reset:U_PURST|                                                                              ; 46 (46)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 32 (32)          ; |top_sin_wave|powerup_reset:U_PURST                                                                                                                                                                                                                                                                                                                ; work         ;
;    |sld_hub:auto_hub|                                                                                   ; 146 (1)     ; 90 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 56 (1)       ; 23 (0)            ; 67 (0)           ; |top_sin_wave|sld_hub:auto_hub                                                                                                                                                                                                                                                                                                                     ; work         ;
;       |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|                                                    ; 145 (103)   ; 90 (62)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 55 (41)      ; 23 (23)           ; 67 (42)          ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst                                                                                                                                                                                                                                                                        ; work         ;
;          |sld_rom_sr:hub_info_reg|                                                                      ; 22 (22)     ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 9 (9)            ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg                                                                                                                                                                                                                                                ; work         ;
;          |sld_shadow_jsm:shadow_jsm|                                                                    ; 20 (20)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 19 (19)          ; |top_sin_wave|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                                                                              ; work         ;
;    |sld_signaltap:auto_signaltap_0|                                                                     ; 1040 (89)   ; 897 (88)                  ; 0 (0)         ; 180224      ; 22   ; 0            ; 0       ; 0         ; 0    ; 0            ; 143 (1)      ; 520 (88)          ; 377 (0)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                                                       ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                           ; 951 (0)     ; 809 (0)                   ; 0 (0)         ; 180224      ; 22   ; 0            ; 0       ; 0         ; 0    ; 0            ; 142 (0)      ; 432 (0)           ; 377 (0)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                                                                 ; work         ;
;          |sld_signaltap_implb:sld_signaltap_body|                                                       ; 951 (326)   ; 809 (260)                 ; 0 (0)         ; 180224      ; 22   ; 0            ; 0       ; 0         ; 0    ; 0            ; 142 (66)     ; 432 (203)         ; 377 (55)         ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body                                                                                                                                                                                                                          ; work         ;
;             |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                            ; 78 (76)     ; 76 (76)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 51 (51)           ; 26 (0)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                           ; work         ;
;                |lpm_decode:wdecoder|                                                                    ; 2 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 1 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                       ; work         ;
;                   |decode_4uf:auto_generated|                                                           ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated                                                                                                             ; work         ;
;                |lpm_mux:mux|                                                                            ; 25 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (0)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux                                                                                                                                               ; work         ;
;                   |mux_krc:auto_generated|                                                              ; 25 (25)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (25)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_krc:auto_generated                                                                                                                        ; work         ;
;             |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 180224      ; 22   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                          ; work         ;
;                |altsyncram_nq14:auto_generated|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 180224      ; 22   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_nq14:auto_generated                                                                                                                                           ; work         ;
;             |lpm_shiftreg:segment_offset_config_deserialize|                                            ; 12 (12)     ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 11 (11)           ; 1 (1)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                           ; work         ;
;             |lpm_shiftreg:status_register|                                                              ; 17 (17)     ; 17 (17)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 17 (17)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                             ; work         ;
;             |serial_crc_16:\tdo_crc_gen:tdo_crc_calc|                                                   ; 14 (14)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 10 (10)           ; 3 (3)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc                                                                                                                                                                                  ; work         ;
;             |sld_buffer_manager:sld_buffer_manager_inst|                                                ; 105 (105)   ; 69 (69)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (33)      ; 12 (12)           ; 60 (60)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                               ; work         ;
;             |sld_ela_control:ela_control|                                                               ; 250 (1)     ; 236 (1)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (0)       ; 145 (0)           ; 91 (1)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                              ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                                ; 4 (4)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 0 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                      ; work         ;
;                |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 220 (0)     ; 220 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 132 (0)           ; 88 (0)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                       ; work         ;
;                   |lpm_shiftreg:trigger_condition_deserialize|                                          ; 132 (132)   ; 132 (132)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 88 (88)           ; 44 (44)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                            ; work         ;
;                   |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 132 (0)     ; 88 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 44 (0)            ; 88 (0)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                        ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                           ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1  ; work         ;
;                      |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 2 (2)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1  ; work         ;
;                |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                          ; 25 (15)     ; 11 (1)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 9 (0)             ; 2 (1)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                ; work         ;
;                   |lpm_shiftreg:trigger_config_deserialize|                                             ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 1 (1)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                        ; work         ;
;             |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 134 (10)    ; 118 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (10)      ; 0 (0)             ; 118 (0)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                         ; work         ;
;                |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 8 (0)       ; 6 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 6 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                               ; work         ;
;                   |cntr_9fi:auto_generated|                                                             ; 8 (8)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 6 (6)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated                                                       ; work         ;
;                |lpm_counter:read_pointer_counter|                                                       ; 12 (0)      ; 12 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 12 (0)           ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                        ; work         ;
;                   |cntr_d8j:auto_generated|                                                             ; 12 (12)     ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 12 (12)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated                                                                                ; work         ;
;                |lpm_counter:status_advance_pointer_counter|                                             ; 7 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 5 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                              ; work         ;
;                   |cntr_7fi:auto_generated|                                                             ; 7 (7)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 5 (5)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated                                                                      ; work         ;
;                |lpm_counter:status_read_pointer_counter|                                                ; 3 (0)       ; 1 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 1 (0)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter                                                                                                 ; work         ;
;                   |cntr_p1j:auto_generated|                                                             ; 3 (3)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_p1j:auto_generated                                                                         ; work         ;
;                |lpm_shiftreg:info_data_shift_out|                                                       ; 25 (25)     ; 25 (25)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (25)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                        ; work         ;
;                |lpm_shiftreg:ram_data_shift_out|                                                        ; 44 (44)     ; 44 (44)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 44 (44)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                         ; work         ;
;                |lpm_shiftreg:status_data_shift_out|                                                     ; 25 (25)     ; 25 (25)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (25)          ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                      ; work         ;
;             |sld_rom_sr:crc_rom_sr|                                                                     ; 19 (19)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 8 (8)            ; |top_sin_wave|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                    ; work         ;
+---------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                        ;
+------------+----------+---------------+---------------+-----------------------+-----+------+
; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+------------+----------+---------------+---------------+-----------------------+-----+------+
; CLKOUT     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[7]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[8]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[9]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[10] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SINOUT[11] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; CLK        ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; BUTRST     ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; BUTUP      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; BUTDOWN    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+------------+----------+---------------+---------------+-----------------------+-----+------+


+------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                               ;
+------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                            ; Pad To Core Index ; Setting ;
+------------------------------------------------+-------------------+---------+
; CLK                                            ;                   ;         ;
; BUTRST                                         ;                   ;         ;
;      - button_in_out:U_BUTRST|button_in_d1R~0  ; 1                 ; 6       ;
; BUTUP                                          ;                   ;         ;
;      - button_in_out:U_BUTUP|button_in_d1R~0   ; 1                 ; 6       ;
; BUTDOWN                                        ;                   ;         ;
;      - button_in_out:U_BUTDOWN|button_in_d1R~0 ; 0                 ; 6       ;
+------------------------------------------------+-------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                                                                                                                                                                                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; CLK                                                                                                                                                                                                                                                                                                 ; PIN_G21            ; 715     ; Clock                      ; yes    ; Global Clock         ; GCLK9            ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                                                                                                                                                                                                        ; JTAG_X1_Y15_N0     ; 502     ; Clock                      ; yes    ; Global Clock         ; GCLK1            ; --                        ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                                                        ; JTAG_X1_Y15_N0     ; 23      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; button_in_out:U_BUTDOWN|LessThan0~5                                                                                                                                                                                                                                                                 ; LCCOMB_X27_Y12_N30 ; 20      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; button_in_out:U_BUTRST|Equal0~2                                                                                                                                                                                                                                                                     ; LCCOMB_X27_Y12_N26 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; button_in_out:U_BUTRST|Equal1~5                                                                                                                                                                                                                                                                     ; LCCOMB_X28_Y12_N10 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; button_in_out:U_BUTRST|Equal2~1                                                                                                                                                                                                                                                                     ; LCCOMB_X28_Y12_N6  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; button_in_out:U_BUTRST|Equal3~3                                                                                                                                                                                                                                                                     ; LCCOMB_X28_Y12_N24 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; generate_freq_word:U_GFQWD|FQWD[11]~32                                                                                                                                                                                                                                                              ; LCCOMB_X23_Y11_N6  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; generate_freq_word:U_GFQWD|FQWD[28]~55                                                                                                                                                                                                                                                              ; LCCOMB_X23_Y11_N22 ; 19      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; generate_freq_word:U_GFQWD|FWEN                                                                                                                                                                                                                                                                     ; FF_X23_Y11_N21     ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; powerup_reset:U_PURST|LessThan0~13                                                                                                                                                                                                                                                                  ; LCCOMB_X31_Y18_N2  ; 33      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; rst_W                                                                                                                                                                                                                                                                                               ; LCCOMB_X29_Y12_N18 ; 113     ; Async. clear               ; yes    ; Global Clock         ; GCLK5            ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                               ; FF_X30_Y22_N29     ; 26      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0                                                                                                                                                                                                                    ; LCCOMB_X30_Y25_N6  ; 4       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena                                                                                                                                                                                                                      ; LCCOMB_X30_Y25_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0                                                                                                                                                                                                                    ; LCCOMB_X31_Y24_N6  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~1                                                                                                                                                                                                       ; LCCOMB_X30_Y25_N14 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0                                                                                                                                                                                                      ; LCCOMB_X30_Y25_N8  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~0                                                                                                                                                                                                                       ; LCCOMB_X29_Y24_N30 ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                         ; FF_X29_Y24_N25     ; 27      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][7]                                                                                                                                                                                                                         ; FF_X29_Y24_N23     ; 30      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]~5                                                                                                                                                                                                                         ; LCCOMB_X30_Y24_N26 ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~7                                                                                                                                                                                                                   ; LCCOMB_X29_Y25_N30 ; 5       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~8                                                                                                                                                                                                                   ; LCCOMB_X32_Y25_N6  ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~17                                                                                                                                                                                                 ; LCCOMB_X30_Y22_N10 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~13                                                                                                                                                                                            ; LCCOMB_X29_Y22_N24 ; 5       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~20                                                                                                                                                                                            ; LCCOMB_X30_Y22_N12 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                    ; FF_X32_Y25_N1      ; 15      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                   ; FF_X32_Y25_N11     ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                    ; FF_X32_Y25_N21     ; 45      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                    ; FF_X30_Y22_N19     ; 12      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0                                                                                                                                                                                                             ; LCCOMB_X32_Y25_N14 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                   ; FF_X32_Y25_N23     ; 25      ; Async. clear, Clock enable ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated|eq_node[0]~1                                                               ; LCCOMB_X24_Y22_N0  ; 25      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated|eq_node[1]~0                                                               ; LCCOMB_X24_Y22_N2  ; 25      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed                                                                                                                                                             ; FF_X28_Y23_N7      ; 25      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|collect_data                                                                                                                                                                            ; LCCOMB_X28_Y23_N28 ; 31      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~0                                                                                                                                                                             ; LCCOMB_X27_Y24_N20 ; 32      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all                                                                                                                                                                               ; FF_X23_Y21_N17     ; 324     ; Async. clear               ; yes    ; Global Clock         ; GCLK10           ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[5]~2                                                                                                                                       ; LCCOMB_X17_Y23_N20 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[0]~0                                                                                                                                 ; LCCOMB_X29_Y23_N14 ; 13      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~4                                                                                                                          ; LCCOMB_X28_Y23_N20 ; 26      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0                                                                                                           ; LCCOMB_X28_Y23_N0  ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|Equal2~1                                                                                               ; LCCOMB_X27_Y19_N4  ; 1       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset                                                                                     ; LCCOMB_X26_Y18_N24 ; 12      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[5]~0 ; LCCOMB_X26_Y18_N8  ; 6       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[4]~0                ; LCCOMB_X27_Y19_N20 ; 5       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_p1j:auto_generated|counter_reg_bit[0]~0                   ; LCCOMB_X26_Y19_N0  ; 1       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena                                                                           ; LCCOMB_X26_Y18_N26 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3]~15                                                                                                                                                     ; LCCOMB_X26_Y25_N26 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]~8                                                                                                                                                 ; LCCOMB_X26_Y25_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|status_shift_enable~0                                                                                                                                                                   ; LCCOMB_X28_Y24_N14 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_gen~0                                                                                                                                                                           ; LCCOMB_X27_Y24_N28 ; 14      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[14]~1                                                                                                                                                                   ; LCCOMB_X17_Y23_N18 ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[0]~1                                                                                                                                                              ; LCCOMB_X27_Y24_N0  ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_setup_ena                                                                                                                                                                       ; LCCOMB_X27_Y24_N8  ; 158     ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                                                       ;
+-----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                                                  ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; CLK                                                                                                                   ; PIN_G21            ; 715     ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                          ; JTAG_X1_Y15_N0     ; 502     ; 0                                    ; Global Clock         ; GCLK1            ; --                        ;
; rst_W                                                                                                                 ; LCCOMB_X29_Y12_N18 ; 113     ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all ; FF_X23_Y21_N17     ; 324     ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
+-----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                                                                                                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                                                                                                                                                                                                                               ; Fan-Out ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_setup_ena                                                                                                                                                                                                                      ; 158     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sdr                                                                                                                                                                                                                                    ; 61      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed                                                                                                                                                                                                            ; 47      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load~0                                                                                                                                      ; 45      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                                                                   ; 45      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][8]                                                                                                                                                                                                                                                                        ; 38      ;
; powerup_reset:U_PURST|LessThan0~13                                                                                                                                                                                                                                                                                                                 ; 33      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[14]~1                                                                                                                                                                                                                  ; 32      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~0                                                                                                                                                                                                                            ; 32      ;
; generate_freq_word:U_GFQWD|FWEN                                                                                                                                                                                                                                                                                                                    ; 32      ;
; generate_freq_word:U_GFQWD|FQWD[11]~32                                                                                                                                                                                                                                                                                                             ; 32      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|collect_data                                                                                                                                                                                                                           ; 31      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][7]                                                                                                                                                                                                                                                                        ; 30      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                                                                   ; 29      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                                                                                                                                                        ; 27      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~4                                                                                                                                                                         ; 26      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_ram_shift_load~0                                                                                                                               ; 26      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                                                                              ; 26      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated|eq_node[0]~1                                                                                                              ; 25      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_4uf:auto_generated|eq_node[1]~0                                                                                                              ; 25      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|xraddr[0]                                                                                                                                                               ; 25      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                                                                  ; 25      ;
; sld_signaltap:auto_signaltap_0|~GND                                                                                                                                                                                                                                                                                                                ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[11]                                                                                                                                                                                                       ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[10]                                                                                                                                                                                                       ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[9]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[8]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[7]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[6]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[5]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[4]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[3]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[2]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[1]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[0]                                                                                                                                                                                                        ; 24      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[11]                                                                          ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[10]                                                                          ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[9]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[8]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[7]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[6]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[5]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[4]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[3]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[2]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[1]                                                                           ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_d8j:auto_generated|counter_reg_bit[0]                                                                           ; 23      ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                                                                                                       ; 23      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~8                                                                                                                                                                                    ; 20      ;
; ~GND                                                                                                                                                                                                                                                                                                                                               ; 20      ;
; button_in_out:U_BUTDOWN|LessThan0~5                                                                                                                                                                                                                                                                                                                ; 20      ;
; generate_freq_word:U_GFQWD|FQWD[28]~55                                                                                                                                                                                                                                                                                                             ; 19      ;
; generate_freq_word:U_GFQWD|butdown_enR                                                                                                                                                                                                                                                                                                             ; 19      ;
; generate_freq_word:U_GFQWD|butup_enR                                                                                                                                                                                                                                                                                                               ; 19      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal0~3                                                                                                                                                                                    ; 18      ;
; generate_freq_word:U_GFQWD|always1~0                                                                                                                                                                                                                                                                                                               ; 18      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|status_shift_enable~0                                                                                                                                                                                                                  ; 17      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|status_load_on~0                                                                                                                                                                                                                       ; 17      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[0]~1                                                                                                                                                                                                             ; 16      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|process_0~0                                                                                                                                                                                 ; 15      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                                                                   ; 15      ;
; generate_freq_word:U_GFQWD|Equal1~5                                                                                                                                                                                                                                                                                                                ; 15      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~0                                                                                                                                                                         ; 14      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_gen~0                                                                                                                                                                                                                          ; 14      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|cdr~0                                                                                                                                                                                                                                  ; 14      ;
; altera_internal_jtag~TDIUTAP                                                                                                                                                                                                                                                                                                                       ; 14      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[0]~0                                                                                                                                                                                ; 13      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[5]~2                                                                                                                                                                                      ; 13      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[10]                                                                                                                                                                                                                                                                         ; 13      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena                                                                                                                          ; 12      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset                                                                                                                                    ; 12      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0                                                                                                                                                          ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                                                                   ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                                                                  ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                                                                     ; 11      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~0                                                                                                                                                                                                                                                                      ; 10      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]                                                                                                                                                                                                  ; 9       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]~5                                                                                                                                                                                                                                                                        ; 9       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                                                                        ; 9       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set                                                                                                                                                                           ; 8       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|crc_rom_sr_ena~0                                                                                                                                                                                                                       ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                                                                          ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                                                                    ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                                                                                                                                                    ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                                                                                                                                                    ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                                                                                                                                                    ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                                                                                                                                                    ; 8       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[1]                                                                                                                                                                                                  ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                                                                                                                                                  ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                                                                          ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                                                                          ; 7       ;
; generate_freq_word:U_GFQWD|Equal0~10                                                                                                                                                                                                                                                                                                               ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[9]                                                                                                                                                                                                                                                                                                                 ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[8]                                                                                                                                                                                                                                                                                                                 ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[5]                                                                                                                                                                                                                                                                                                                 ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[3]                                                                                                                                                                                                                                                                                                                 ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[29]                                                                                                                                                                                                                                                                                                                ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[28]                                                                                                                                                                                                                                                                                                                ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[25]                                                                                                                                                                                                                                                                                                                ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[21]                                                                                                                                                                                                                                                                                                                ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[1]                                                                                                                                                                                                                                                                                                                 ; 7       ;
; generate_freq_word:U_GFQWD|FQWD[16]                                                                                                                                                                                                                                                                                                                ; 7       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[5]~0                                                ; 6       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                                                                                                                                        ; 6       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|run                                                                                                                                                                                                                                    ; 6       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|clear_signal                                                                                                                                                                                                     ; 6       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[2]                                                                                                                                                                                                  ; 6       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal                                                                                                                                                                                                                                                 ; 6       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][9]                                                                                                                                                                                                                                                                        ; 6       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                                                                                                                                              ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[6]                                                                                                                                                                                                                                                                                                                 ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[4]                                                                                                                                                                                                                                                                                                                 ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[26]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[19]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[18]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[15]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[11]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[0]                                                                                                                                                                                                                                                                                                                 ; 6       ;
; button_in_out:U_BUTDOWN|counterR[16]                                                                                                                                                                                                                                                                                                               ; 6       ;
; button_in_out:U_BUTDOWN|counterR[17]                                                                                                                                                                                                                                                                                                               ; 6       ;
; button_in_out:U_BUTDOWN|counterR[5]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[7]                                                                                                                                                                                                                                                                                                                 ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[31]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[30]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[2]                                                                                                                                                                                                                                                                                                                 ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[27]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[23]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[22]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[14]                                                                                                                                                                                                                                                                                                                ; 6       ;
; generate_freq_word:U_GFQWD|FQWD[10]                                                                                                                                                                                                                                                                                                                ; 6       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[4]~0                                                               ; 5       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[3]                                                                                                                                                                                                  ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~20                                                                                                                                                                                                                                           ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~13                                                                                                                                                                                                                                           ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~8                                                                                                                                                                                                                                                                  ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~7                                                                                                                                                                                                                                                                  ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                                                                                                                                                          ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0                                                                                                                                                                                                                                                                   ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                                                                                                                                                        ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                                                                                                                                                              ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                                                                                                                                              ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                                                                                                                                              ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[24]                                                                                                                                                                                                                                                                                                                ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[20]                                                                                                                                                                                                                                                                                                                ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[17]                                                                                                                                                                                                                                                                                                                ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[13]                                                                                                                                                                                                                                                                                                                ; 5       ;
; generate_freq_word:U_GFQWD|FQWD[12]                                                                                                                                                                                                                                                                                                                ; 5       ;
; button_in_out:U_BUTDOWN|counterR[8]                                                                                                                                                                                                                                                                                                                ; 5       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]~8                                                                                                                                                                                                ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3]~15                                                                                                                                                                                                    ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|condition_delay_reg[3]                                                                                                                                                                                                                 ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:is_buffer_wrapped                                                                                                                                                           ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize|dffs[0]                                                                                              ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|last_level_delayed                                                                                                                           ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~17                                                                                                                                                                                                                                                ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~1                                                                                                                                                                                                                                                      ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0                                                                                                                                                                                                                                                     ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena                                                                                                                                                                                                                                                                     ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0                                                                                                                                                                                                                                                                   ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]~8                                                                                                                                                                                                                                                                 ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                                                                      ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg_proc~0                                                                                                                                                                                                                                                                 ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][6]                                                                                                                                                                                                                                                                        ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                                                                                                                                              ; 4       ;
; button_in_out:U_BUTDOWN|button_in_d2R                                                                                                                                                                                                                                                                                                              ; 4       ;
; button_in_out:U_BUTUP|button_in_d2R                                                                                                                                                                                                                                                                                                                ; 4       ;
; button_in_out:U_BUTRST|button_in_d2R                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[2]                                                                                                                                                                                                                                                                                                                ; 4       ;
; button_in_out:U_BUTDOWN|counterR[6]                                                                                                                                                                                                                                                                                                                ; 4       ;
; button_in_out:U_BUTDOWN|counterR[7]                                                                                                                                                                                                                                                                                                                ; 4       ;
; button_in_out:U_BUTDOWN|counterR[12]                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[10]                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[14]                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[15]                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[18]                                                                                                                                                                                                                                                                                                               ; 4       ;
; button_in_out:U_BUTDOWN|counterR[13]                                                                                                                                                                                                                                                                                                               ; 4       ;
; powerup_reset:U_PURST|counterR[22]                                                                                                                                                                                                                                                                                                                 ; 4       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~11                                                                                                                                                                             ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~10                                                                                                                                                                             ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~9                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~8                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~7                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~6                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~5                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~4                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~3                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~2                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~1                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[89]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[92]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[95]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[98]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[101]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[104]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[107]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[110]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[113]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[116]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[119]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[122]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[131]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[41]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[44]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[47]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[50]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[53]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[56]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[59]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[62]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[65]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[68]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[71]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[74]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[77]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[80]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[83]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[86]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[125]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[128]                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[5]                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[8]                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[11]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[14]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[2]                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[17]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[20]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[23]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[29]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[32]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[35]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[38]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~0                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_segment_delayed[0]                                                                                                                                                                                                             ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0]~4                                                                                                                                                                                                ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~9                                                                                                                                                                                                        ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr~0                                                                                                                                                                                         ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~1                                                                                                                                                                                                                            ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~6                                                                                                                                                                                                        ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[43]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[42]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[41]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[40]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[39]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[38]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[37]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[36]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[35]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[34]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[33]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[32]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[31]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[30]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[29]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[28]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[27]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[26]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[25]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[24]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[23]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[21]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[20]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[19]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[18]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[17]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[16]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[15]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[12]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[11]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[10]                                                                                                                                                                                                                                                                                              ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[9]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[8]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[7]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[6]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[4]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[2]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[0]                                                                                                                                                                                                                                                                                               ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|bypass_reg_out                                                                                                                                                                                                                         ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[0]                                                                                                                                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[0]                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_p1j:auto_generated|counter_reg_bit[0]                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[12]                                                                                                                                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[11]                                                                                                                                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10]                                                                                                                                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[9]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[8]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[7]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[5]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[4]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[0]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[3]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[2]                                                                                                                                                                                  ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[2]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[1]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[3]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[4]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_7fi:auto_generated|counter_reg_bit[0]                                                                 ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[13]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[7]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[31]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[30]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[29]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[28]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[27]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[26]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[25]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[24]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[23]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[22]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[21]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[20]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[19]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[18]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[17]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[15]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[10]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[2]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[3]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[4]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[5]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[16]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[6]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[8]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[9]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[11]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[12]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[14]                                                                                                                                                                                                                    ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[1]                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[0]                                                                                                                                                                                                                     ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                                                                 ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~6                                                                                                                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                                                                      ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0                                                                                                                                                                                                                                                            ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                                                                       ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                                                                                                                                                  ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                                                                                                                                                   ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                                                                                                                                                   ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                                                                   ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                                                                        ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                                                                   ; 3       ;
; button_in_out:U_BUTRST|Equal0~2                                                                                                                                                                                                                                                                                                                    ; 3       ;
; button_in_out:U_BUTRST|Equal1~5                                                                                                                                                                                                                                                                                                                    ; 3       ;
; button_in_out:U_BUTRST|Equal2~1                                                                                                                                                                                                                                                                                                                    ; 3       ;
; button_in_out:U_BUTRST|Equal3~3                                                                                                                                                                                                                                                                                                                    ; 3       ;
; button_in_out:U_BUTDOWN|buttonOutR                                                                                                                                                                                                                                                                                                                 ; 3       ;
; button_in_out:U_BUTUP|buttonOutR                                                                                                                                                                                                                                                                                                                   ; 3       ;
; button_in_out:U_BUTDOWN|counterR[4]                                                                                                                                                                                                                                                                                                                ; 3       ;
; button_in_out:U_BUTDOWN|counterR[3]                                                                                                                                                                                                                                                                                                                ; 3       ;
; button_in_out:U_BUTDOWN|counterR[11]                                                                                                                                                                                                                                                                                                               ; 3       ;
; button_in_out:U_BUTDOWN|counterR[19]                                                                                                                                                                                                                                                                                                               ; 3       ;
; button_in_out:U_BUTDOWN|counterR[9]                                                                                                                                                                                                                                                                                                                ; 3       ;
; dds_core_sin:U_DDS|sinout_R[10]                                                                                                                                                                                                                                                                                                                    ; 3       ;
; dds_core_sin:U_DDS|sinout_R[11]                                                                                                                                                                                                                                                                                                                    ; 3       ;
; dds_core_sin:U_DDS|sinout_R[9]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; powerup_reset:U_PURST|counterR[10]                                                                                                                                                                                                                                                                                                                 ; 3       ;
; powerup_reset:U_PURST|counterR[13]                                                                                                                                                                                                                                                                                                                 ; 3       ;
; powerup_reset:U_PURST|counterR[12]                                                                                                                                                                                                                                                                                                                 ; 3       ;
; powerup_reset:U_PURST|counterR[19]                                                                                                                                                                                                                                                                                                                 ; 3       ;
; powerup_reset:U_PURST|counterR[18]                                                                                                                                                                                                                                                                                                                 ; 3       ;
; dds_core_sin:U_DDS|sinout_R[1]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[2]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[3]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[4]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[5]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[6]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[7]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[8]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; dds_core_sin:U_DDS|sinout_R[0]                                                                                                                                                                                                                                                                                                                     ; 3       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|Equal0~1                                                                                                                                              ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[11]                                                                                                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[10]                                                                                                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[11]                                                                                                                                                                                                       ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[9]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[10]                                                                                                                                                                                                       ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[8]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[9]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[7]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[8]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[6]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[7]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[5]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[6]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[4]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[5]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[3]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[4]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[2]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[3]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[1]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[2]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:last_trigger_address_var[0]                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[1]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0                                                                                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|last_trigger_address_delayed[0]                                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[88]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[87]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[91]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[90]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[94]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[93]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[97]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[96]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[100]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[99]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[103]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[102]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[106]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[105]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[109]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[108]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[112]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[111]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[115]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[114]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[118]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[117]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[121]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[120]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[130]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[129]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[40]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[39]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[43]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[42]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[46]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[45]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[49]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[48]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[52]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[51]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[55]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[54]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[58]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[57]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[61]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[60]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[64]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[63]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[67]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[66]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[70]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[69]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[73]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[72]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[76]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[75]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[79]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[78]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[82]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[81]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[85]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[84]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[124]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[123]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[127]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[126]                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[4]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[3]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[7]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[6]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[10]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[9]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[13]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[12]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[1]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[0]                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[16]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[15]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[19]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[18]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[22]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[21]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[25]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[24]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[28]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[27]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[31]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[30]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[34]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[33]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[37]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[36]                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[11]                                                                                                                                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[10]                                                                                                                                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[9]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[8]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[7]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[6]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[5]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[4]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:segment_shift_var                                                                                                                                                           ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|segment_wrapped_delayed                                                                                                                                                                                                                ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[3]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[11]                                                                                                                                                            ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[10]                                                                                                                                                            ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[9]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[8]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[7]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[6]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[5]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[4]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[3]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[2]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[1]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[0]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0]                                                                                                                                                            ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~2                                                                                                                                                                              ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:base_address[0]                                                                                                                                                             ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[2]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|state_status[2]~1                                                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|state_status[2]~0                                                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_out_mode_ff                                                                                                                                                                                                                    ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:collecting_post_data_var                                                                                                                                                    ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig                                                                                                                                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all                                                                                                                                                                                                                              ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize|dffs[1]                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|LessThan0~9                                                                                                                                                                                                                            ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|LessThan0~4                                                                                                                                                                                                                            ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_internal~7                                                                                                                                                                                                                         ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_internal~2                                                                                                                                                                                                                         ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_internal~1                                                                                                                                                                                                                         ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[2]                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[3]                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[4]                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[5]                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9fi:auto_generated|counter_reg_bit[1]                                                  ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[12]                                                                                                                                                                                       ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[11]                                                                                                                                                                                       ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[10]                                                                                                                                                                                       ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[9]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[8]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[7]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[6]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[5]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[4]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[3]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[2]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~22                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~20                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~18                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~16                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~14                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~12                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~10                                                                                                                                                                                     ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~8                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~6                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~4                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~2                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Add2~0                                                                                                                                                                                      ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[1]                                                                                                                                                                                        ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[0]                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~9                                                                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~0                                                                                                                                                                                                                                                      ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~9                                                                                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal3~0                                                                                                                                                                                                                                                                             ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]~0                                                                                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~4                                                                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]~7                                                                                                                                                                                                                                                                 ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~4                                                                                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~1                                                                                                                                                                                                                                                                             ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~0                                                                                                                                                                                                                                                                             ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                                                                      ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1                                                                                                                                                                                                                                                                      ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[9]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[8]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[7]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                                                                          ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][5]                                                                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                                                                 ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                                                                 ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                                                                   ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[6]~_wirecell                                                                                                                                                                                                                                                                                                       ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[4]~_wirecell                                                                                                                                                                                                                                                                                                       ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[26]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[24]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[20]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[19]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[18]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[17]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[15]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[13]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[12]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[11]~_wirecell                                                                                                                                                                                                                                                                                                      ; 2       ;
; generate_freq_word:U_GFQWD|FQWD[0]~_wirecell                                                                                                                                                                                                                                                                                                       ; 2       ;
; button_in_out:U_BUTRST|Equal1~3                                                                                                                                                                                                                                                                                                                    ; 2       ;
; button_in_out:U_BUTRST|Equal3~1                                                                                                                                                                                                                                                                                                                    ; 2       ;
; button_in_out:U_BUTDOWN|LessThan0~1                                                                                                                                                                                                                                                                                                                ; 2       ;
; button_in_out:U_BUTRST|Equal1~1                                                                                                                                                                                                                                                                                                                    ; 2       ;
; button_in_out:U_BUTRST|Equal1~0                                                                                                                                                                                                                                                                                                                    ; 2       ;
; dds_core_sin:U_DDS|addr_R[9]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[8]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[7]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[6]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[5]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[4]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[3]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[2]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[1]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|addr_R[0]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; generate_freq_word:U_GFQWD|Equal0~4                                                                                                                                                                                                                                                                                                                ; 2       ;
; powerup_reset:U_PURST|LessThan0~9                                                                                                                                                                                                                                                                                                                  ; 2       ;
; button_in_out:U_BUTRST|buttonOutR                                                                                                                                                                                                                                                                                                                  ; 2       ;
; button_in_out:U_BUTDOWN|counterR[0]                                                                                                                                                                                                                                                                                                                ; 2       ;
; button_in_out:U_BUTDOWN|counterR[1]                                                                                                                                                                                                                                                                                                                ; 2       ;
; dds_core_sin:U_DDS|acc_R[31]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[30]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[29]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[28]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[27]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[26]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[25]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[24]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[23]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; dds_core_sin:U_DDS|acc_R[22]                                                                                                                                                                                                                                                                                                                       ; 2       ;
; powerup_reset:U_PURST|counterR[5]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[4]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[3]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[2]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[1]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[0]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[6]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[7]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[9]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[8]                                                                                                                                                                                                                                                                                                                  ; 2       ;
; powerup_reset:U_PURST|counterR[11]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[14]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[17]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[16]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[15]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[30]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[29]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[28]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[27]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[31]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[21]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[20]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[26]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[25]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[24]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; powerup_reset:U_PURST|counterR[23]                                                                                                                                                                                                                                                                                                                 ; 2       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|condition_delay_reg[0]~feeder                                                                                                                                                                                                          ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~feeder                                                                                                                                                                    ; 1       ;
; altera_reserved_tdi~input                                                                                                                                                                                                                                                                                                                          ; 1       ;
; altera_reserved_tck~input                                                                                                                                                                                                                                                                                                                          ; 1       ;
; altera_reserved_tms~input                                                                                                                                                                                                                                                                                                                          ; 1       ;
; BUTDOWN~input                                                                                                                                                                                                                                                                                                                                      ; 1       ;
; BUTUP~input                                                                                                                                                                                                                                                                                                                                        ; 1       ;
; BUTRST~input                                                                                                                                                                                                                                                                                                                                       ; 1       ;
; CLK~input                                                                                                                                                                                                                                                                                                                                          ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed~0                                                                                                                                                                                                          ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|p_match_out~1  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|p_match_out~0  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|p_match_out~1 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|p_match_out~0 ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~16                                                                                                                                                                                                       ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter~9                                                                                                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~3                                                                                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][43]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][42]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][43]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][41]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][42]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][43]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][40]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][41]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][42]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][43]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][39]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][40]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][41]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][42]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~43                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][38]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][39]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][40]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][41]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~42                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[43]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][37]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][38]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][39]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][40]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~41                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[42]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][36]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][37]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][38]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][39]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~40                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[41]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][35]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][36]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][37]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][38]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~39                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[40]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][34]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][35]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][36]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][37]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~38                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[39]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][33]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][34]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][35]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][36]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~37                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[38]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][32]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][33]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][34]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][35]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~36                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[37]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][31]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][32]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][33]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][34]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~35                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[36]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][30]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][31]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][32]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][33]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~34                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[35]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][29]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][30]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][31]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][32]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~33                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[34]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][28]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][29]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][30]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][31]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~32                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[33]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][27]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][28]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][29]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][30]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~31                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[32]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][26]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][27]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][28]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][29]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~30                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[31]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][25]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][26]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][27]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][28]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~29                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[30]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][24]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][25]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][26]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][27]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~28                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[29]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][23]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][24]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][25]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][26]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~27                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[28]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][22]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][23]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][24]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][25]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~26                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[27]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][21]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][22]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][23]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][24]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~25                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[26]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][20]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][21]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][22]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][23]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~24                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[25]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][19]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][20]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][21]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][22]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~23                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[24]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][18]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][19]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][20]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][21]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~22                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[23]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][17]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][18]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][19]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][20]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~21                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[22]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][16]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][17]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][18]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][19]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~20                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[21]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][15]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][16]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][17]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][18]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~19                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[20]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][14]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][15]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][16]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][17]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~18                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[19]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][13]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][14]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][15]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][16]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~17                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[18]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][12]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][13]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][14]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][15]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~16                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[17]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][11]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][12]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][13]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][14]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~15                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[16]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][10]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][11]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][12]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][13]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~14                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[15]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][9]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][10]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][11]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][12]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~13                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[14]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][8]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][9]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][10]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][11]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~12                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[13]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][7]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][8]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][9]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][10]                                                                                                                                                                                                            ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~11                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[12]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][6]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][7]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][8]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][9]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~10                                                                                                                  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[11]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][5]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][6]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][7]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][8]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~9                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[10]                                                                                                              ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][4]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][5]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][6]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][7]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~8                                                                                                                   ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[9]                                                                                                               ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[0][3]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[1][4]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[2][5]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|acq_data_in_pipe_reg[3][6]                                                                                                                                                                                                             ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|_~7                                                                                                                   ; 1       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; Name                                                                                                                                                                                                  ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF                                                ; Location                                                                                                                                                                                                                                                                                                                                                      ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
; dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ALTSYNCRAM                                                                                              ; AUTO ; ROM              ; Single Clock ; 1024         ; 12           ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 12288  ; 1024                        ; 12                          ; --                          ; --                          ; 12288               ; 2    ; db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif ; M9K_X13_Y21_N0, M9K_X13_Y19_N0                                                                                                                                                                                                                                                                                                                                ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_nq14:auto_generated|ALTSYNCRAM ; M9K  ; Simple Dual Port ; Dual Clocks  ; 4096         ; 44           ; 4096         ; 44           ; yes                    ; no                      ; yes                    ; no                      ; 180224 ; 4096                        ; 44                          ; 4096                        ; 44                          ; 180224              ; 22   ; None                                               ; M9K_X13_Y23_N0, M9K_X25_Y23_N0, M9K_X25_Y19_N0, M9K_X25_Y21_N0, M9K_X25_Y22_N0, M9K_X25_Y20_N0, M9K_X13_Y20_N0, M9K_X25_Y18_N0, M9K_X25_Y9_N0, M9K_X13_Y16_N0, M9K_X25_Y16_N0, M9K_X25_Y17_N0, M9K_X25_Y10_N0, M9K_X13_Y18_N0, M9K_X25_Y12_N0, M9K_X25_Y13_N0, M9K_X13_Y17_N0, M9K_X13_Y14_N0, M9K_X25_Y11_N0, M9K_X25_Y14_N0, M9K_X25_Y15_N0, M9K_X13_Y15_N0 ; Don't care           ; Old data        ; Old data        ; Yes           ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) 
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |top_sin_wave|dds_core_sin:U_DDS|DDS_CORE_ROM:u_sinrom|altsyncram:Ram0_rtl_0|altsyncram_k581:auto_generated|ALTSYNCRAM                                                                                                                                           ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
;   Addr   ;              +0              ;              +1              ;              +2              ;              +3              ;              +4              ;              +5              ;              +6              ;              +7              ;
+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
;0;(000000000000) (0) (0) (00)    ;(000000001100) (14) (12) (0C)   ;(000000011001) (31) (25) (19)   ;(000000100101) (45) (37) (25)   ;(000000110010) (62) (50) (32)   ;(000000111110) (76) (62) (3E)   ;(000001001011) (113) (75) (4B)   ;(000001010111) (127) (87) (57)   ;
;8;(000001100100) (144) (100) (64)    ;(000001110000) (160) (112) (70)   ;(000001111101) (175) (125) (7D)   ;(000010001010) (212) (138) (8A)   ;(000010010110) (226) (150) (96)   ;(000010100011) (243) (163) (A3)   ;(000010101111) (257) (175) (AF)   ;(000010111100) (274) (188) (BC)   ;
;16;(000011001000) (310) (200) (C8)    ;(000011010101) (325) (213) (D5)   ;(000011100001) (341) (225) (E1)   ;(000011101110) (356) (238) (EE)   ;(000011111010) (372) (250) (FA)   ;(000100000111) (407) (263) (107)   ;(000100010011) (423) (275) (113)   ;(000100011111) (437) (287) (11F)   ;
;24;(000100101100) (454) (300) (12C)    ;(000100111000) (470) (312) (138)   ;(000101000101) (505) (325) (145)   ;(000101010001) (521) (337) (151)   ;(000101011101) (535) (349) (15D)   ;(000101101010) (552) (362) (16A)   ;(000101110110) (566) (374) (176)   ;(000110000011) (603) (387) (183)   ;
;32;(000110001111) (617) (399) (18F)    ;(000110011011) (633) (411) (19B)   ;(000110100111) (647) (423) (1A7)   ;(000110110100) (664) (436) (1B4)   ;(000111000000) (700) (448) (1C0)   ;(000111001100) (714) (460) (1CC)   ;(000111011000) (730) (472) (1D8)   ;(000111100101) (745) (485) (1E5)   ;
;40;(000111110001) (761) (497) (1F1)    ;(000111111101) (775) (509) (1FD)   ;(001000001001) (1011) (521) (209)   ;(001000010101) (1025) (533) (215)   ;(001000100001) (1041) (545) (221)   ;(001000101110) (1056) (558) (22E)   ;(001000111010) (1072) (570) (23A)   ;(001001000110) (1106) (582) (246)   ;
;48;(001001010010) (1122) (594) (252)    ;(001001011110) (1136) (606) (25E)   ;(001001101010) (1152) (618) (26A)   ;(001001110110) (1166) (630) (276)   ;(001010000010) (1202) (642) (282)   ;(001010001110) (1216) (654) (28E)   ;(001010011001) (1231) (665) (299)   ;(001010100101) (1245) (677) (2A5)   ;
;56;(001010110001) (1261) (689) (2B1)    ;(001010111101) (1275) (701) (2BD)   ;(001011001001) (1311) (713) (2C9)   ;(001011010100) (1324) (724) (2D4)   ;(001011100000) (1340) (736) (2E0)   ;(001011101100) (1354) (748) (2EC)   ;(001011111000) (1370) (760) (2F8)   ;(001100000011) (1403) (771) (303)   ;
;64;(001100001111) (1417) (783) (30F)    ;(001100011010) (1432) (794) (31A)   ;(001100100110) (1446) (806) (326)   ;(001100110010) (1462) (818) (332)   ;(001100111101) (1475) (829) (33D)   ;(001101001000) (1510) (840) (348)   ;(001101010100) (1524) (852) (354)   ;(001101011111) (1537) (863) (35F)   ;
;72;(001101101011) (1553) (875) (36B)    ;(001101110110) (1566) (886) (376)   ;(001110000001) (1601) (897) (381)   ;(001110001101) (1615) (909) (38D)   ;(001110011000) (1630) (920) (398)   ;(001110100011) (1643) (931) (3A3)   ;(001110101110) (1656) (942) (3AE)   ;(001110111001) (1671) (953) (3B9)   ;
;80;(001111000100) (1704) (964) (3C4)    ;(001111010000) (1720) (976) (3D0)   ;(001111011011) (1733) (987) (3DB)   ;(001111100110) (1746) (998) (3E6)   ;(001111110000) (1760) (1008) (3F0)   ;(001111111011) (1773) (1019) (3FB)   ;(010000000110) (2006) (1030) (406)   ;(010000010001) (2021) (1041) (411)   ;
;88;(010000011100) (2034) (1052) (41C)    ;(010000100111) (2047) (1063) (427)   ;(010000110001) (2061) (1073) (431)   ;(010000111100) (2074) (1084) (43C)   ;(010001000111) (2107) (1095) (447)   ;(010001010001) (2121) (1105) (451)   ;(010001011100) (2134) (1116) (45C)   ;(010001100110) (2146) (1126) (466)   ;
;96;(010001110001) (2161) (1137) (471)    ;(010001111011) (2173) (1147) (47B)   ;(010010000110) (2206) (1158) (486)   ;(010010010000) (2220) (1168) (490)   ;(010010011010) (2232) (1178) (49A)   ;(010010100100) (2244) (1188) (4A4)   ;(010010101111) (2257) (1199) (4AF)   ;(010010111001) (2271) (1209) (4B9)   ;
;104;(010011000011) (2303) (1219) (4C3)    ;(010011001101) (2315) (1229) (4CD)   ;(010011010111) (2327) (1239) (4D7)   ;(010011100001) (2341) (1249) (4E1)   ;(010011101011) (2353) (1259) (4EB)   ;(010011110101) (2365) (1269) (4F5)   ;(010011111111) (2377) (1279) (4FF)   ;(010100001000) (2410) (1288) (508)   ;
;112;(010100010010) (2422) (1298) (512)    ;(010100011100) (2434) (1308) (51C)   ;(010100100101) (2445) (1317) (525)   ;(010100101111) (2457) (1327) (52F)   ;(010100111001) (2471) (1337) (539)   ;(010101000010) (2502) (1346) (542)   ;(010101001011) (2513) (1355) (54B)   ;(010101010101) (2525) (1365) (555)   ;
;120;(010101011110) (2536) (1374) (55E)    ;(010101100111) (2547) (1383) (567)   ;(010101110001) (2561) (1393) (571)   ;(010101111010) (2572) (1402) (57A)   ;(010110000011) (2603) (1411) (583)   ;(010110001100) (2614) (1420) (58C)   ;(010110010101) (2625) (1429) (595)   ;(010110011110) (2636) (1438) (59E)   ;
;128;(010110100111) (2647) (1447) (5A7)    ;(010110110000) (2660) (1456) (5B0)   ;(010110111001) (2671) (1465) (5B9)   ;(010111000001) (2701) (1473) (5C1)   ;(010111001010) (2712) (1482) (5CA)   ;(010111010011) (2723) (1491) (5D3)   ;(010111011011) (2733) (1499) (5DB)   ;(010111100100) (2744) (1508) (5E4)   ;
;136;(010111101100) (2754) (1516) (5EC)    ;(010111110101) (2765) (1525) (5F5)   ;(010111111101) (2775) (1533) (5FD)   ;(011000000101) (3005) (1541) (605)   ;(011000001110) (3016) (1550) (60E)   ;(011000010110) (3026) (1558) (616)   ;(011000011110) (3036) (1566) (61E)   ;(011000100110) (3046) (1574) (626)   ;
;144;(011000101110) (3056) (1582) (62E)    ;(011000110110) (3066) (1590) (636)   ;(011000111110) (3076) (1598) (63E)   ;(011001000101) (3105) (1605) (645)   ;(011001001101) (3115) (1613) (64D)   ;(011001010101) (3125) (1621) (655)   ;(011001011101) (3135) (1629) (65D)   ;(011001100100) (3144) (1636) (664)   ;
;152;(011001101100) (3154) (1644) (66C)    ;(011001110011) (3163) (1651) (673)   ;(011001111011) (3173) (1659) (67B)   ;(011010000010) (3202) (1666) (682)   ;(011010001001) (3211) (1673) (689)   ;(011010010000) (3220) (1680) (690)   ;(011010010111) (3227) (1687) (697)   ;(011010011111) (3237) (1695) (69F)   ;
;160;(011010100110) (3246) (1702) (6A6)    ;(011010101100) (3254) (1708) (6AC)   ;(011010110011) (3263) (1715) (6B3)   ;(011010111010) (3272) (1722) (6BA)   ;(011011000001) (3301) (1729) (6C1)   ;(011011001000) (3310) (1736) (6C8)   ;(011011001110) (3316) (1742) (6CE)   ;(011011010101) (3325) (1749) (6D5)   ;
;168;(011011011011) (3333) (1755) (6DB)    ;(011011100010) (3342) (1762) (6E2)   ;(011011101000) (3350) (1768) (6E8)   ;(011011101110) (3356) (1774) (6EE)   ;(011011110101) (3365) (1781) (6F5)   ;(011011111011) (3373) (1787) (6FB)   ;(011100000001) (3401) (1793) (701)   ;(011100000111) (3407) (1799) (707)   ;
;176;(011100001101) (3415) (1805) (70D)    ;(011100010011) (3423) (1811) (713)   ;(011100011000) (3430) (1816) (718)   ;(011100011110) (3436) (1822) (71E)   ;(011100100100) (3444) (1828) (724)   ;(011100101010) (3452) (1834) (72A)   ;(011100101111) (3457) (1839) (72F)   ;(011100110101) (3465) (1845) (735)   ;
;184;(011100111010) (3472) (1850) (73A)    ;(011100111111) (3477) (1855) (73F)   ;(011101000101) (3505) (1861) (745)   ;(011101001010) (3512) (1866) (74A)   ;(011101001111) (3517) (1871) (74F)   ;(011101010100) (3524) (1876) (754)   ;(011101011001) (3531) (1881) (759)   ;(011101011110) (3536) (1886) (75E)   ;
;192;(011101100011) (3543) (1891) (763)    ;(011101100111) (3547) (1895) (767)   ;(011101101100) (3554) (1900) (76C)   ;(011101110001) (3561) (1905) (771)   ;(011101110101) (3565) (1909) (775)   ;(011101111010) (3572) (1914) (77A)   ;(011101111110) (3576) (1918) (77E)   ;(011110000011) (3603) (1923) (783)   ;
;200;(011110000111) (3607) (1927) (787)    ;(011110001011) (3613) (1931) (78B)   ;(011110001111) (3617) (1935) (78F)   ;(011110010011) (3623) (1939) (793)   ;(011110010111) (3627) (1943) (797)   ;(011110011011) (3633) (1947) (79B)   ;(011110011111) (3637) (1951) (79F)   ;(011110100011) (3643) (1955) (7A3)   ;
;208;(011110100110) (3646) (1958) (7A6)    ;(011110101010) (3652) (1962) (7AA)   ;(011110101110) (3656) (1966) (7AE)   ;(011110110001) (3661) (1969) (7B1)   ;(011110110100) (3664) (1972) (7B4)   ;(011110111000) (3670) (1976) (7B8)   ;(011110111011) (3673) (1979) (7BB)   ;(011110111110) (3676) (1982) (7BE)   ;
;216;(011111000001) (3701) (1985) (7C1)    ;(011111000100) (3704) (1988) (7C4)   ;(011111000111) (3707) (1991) (7C7)   ;(011111001010) (3712) (1994) (7CA)   ;(011111001101) (3715) (1997) (7CD)   ;(011111001111) (3717) (1999) (7CF)   ;(011111010010) (3722) (2002) (7D2)   ;(011111010101) (3725) (2005) (7D5)   ;
;224;(011111010111) (3727) (2007) (7D7)    ;(011111011010) (3732) (2010) (7DA)   ;(011111011100) (3734) (2012) (7DC)   ;(011111011110) (3736) (2014) (7DE)   ;(011111100000) (3740) (2016) (7E0)   ;(011111100010) (3742) (2018) (7E2)   ;(011111100101) (3745) (2021) (7E5)   ;(011111100110) (3746) (2022) (7E6)   ;
;232;(011111101000) (3750) (2024) (7E8)    ;(011111101010) (3752) (2026) (7EA)   ;(011111101100) (3754) (2028) (7EC)   ;(011111101110) (3756) (2030) (7EE)   ;(011111101111) (3757) (2031) (7EF)   ;(011111110001) (3761) (2033) (7F1)   ;(011111110010) (3762) (2034) (7F2)   ;(011111110011) (3763) (2035) (7F3)   ;
;240;(011111110101) (3765) (2037) (7F5)    ;(011111110110) (3766) (2038) (7F6)   ;(011111110111) (3767) (2039) (7F7)   ;(011111111000) (3770) (2040) (7F8)   ;(011111111001) (3771) (2041) (7F9)   ;(011111111010) (3772) (2042) (7FA)   ;(011111111011) (3773) (2043) (7FB)   ;(011111111011) (3773) (2043) (7FB)   ;
;248;(011111111100) (3774) (2044) (7FC)    ;(011111111101) (3775) (2045) (7FD)   ;(011111111101) (3775) (2045) (7FD)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;
;256;(011111111111) (3777) (2047) (7FF)    ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111110) (3776) (2046) (7FE)   ;(011111111101) (3775) (2045) (7FD)   ;(011111111101) (3775) (2045) (7FD)   ;
;264;(011111111100) (3774) (2044) (7FC)    ;(011111111011) (3773) (2043) (7FB)   ;(011111111011) (3773) (2043) (7FB)   ;(011111111010) (3772) (2042) (7FA)   ;(011111111001) (3771) (2041) (7F9)   ;(011111111000) (3770) (2040) (7F8)   ;(011111110111) (3767) (2039) (7F7)   ;(011111110110) (3766) (2038) (7F6)   ;
;272;(011111110101) (3765) (2037) (7F5)    ;(011111110011) (3763) (2035) (7F3)   ;(011111110010) (3762) (2034) (7F2)   ;(011111110001) (3761) (2033) (7F1)   ;(011111101111) (3757) (2031) (7EF)   ;(011111101110) (3756) (2030) (7EE)   ;(011111101100) (3754) (2028) (7EC)   ;(011111101010) (3752) (2026) (7EA)   ;
;280;(011111101000) (3750) (2024) (7E8)    ;(011111100110) (3746) (2022) (7E6)   ;(011111100101) (3745) (2021) (7E5)   ;(011111100010) (3742) (2018) (7E2)   ;(011111100000) (3740) (2016) (7E0)   ;(011111011110) (3736) (2014) (7DE)   ;(011111011100) (3734) (2012) (7DC)   ;(011111011010) (3732) (2010) (7DA)   ;
;288;(011111010111) (3727) (2007) (7D7)    ;(011111010101) (3725) (2005) (7D5)   ;(011111010010) (3722) (2002) (7D2)   ;(011111001111) (3717) (1999) (7CF)   ;(011111001101) (3715) (1997) (7CD)   ;(011111001010) (3712) (1994) (7CA)   ;(011111000111) (3707) (1991) (7C7)   ;(011111000100) (3704) (1988) (7C4)   ;
;296;(011111000001) (3701) (1985) (7C1)    ;(011110111110) (3676) (1982) (7BE)   ;(011110111011) (3673) (1979) (7BB)   ;(011110111000) (3670) (1976) (7B8)   ;(011110110100) (3664) (1972) (7B4)   ;(011110110001) (3661) (1969) (7B1)   ;(011110101110) (3656) (1966) (7AE)   ;(011110101010) (3652) (1962) (7AA)   ;
;304;(011110100110) (3646) (1958) (7A6)    ;(011110100011) (3643) (1955) (7A3)   ;(011110011111) (3637) (1951) (79F)   ;(011110011011) (3633) (1947) (79B)   ;(011110010111) (3627) (1943) (797)   ;(011110010011) (3623) (1939) (793)   ;(011110001111) (3617) (1935) (78F)   ;(011110001011) (3613) (1931) (78B)   ;
;312;(011110000111) (3607) (1927) (787)    ;(011110000011) (3603) (1923) (783)   ;(011101111110) (3576) (1918) (77E)   ;(011101111010) (3572) (1914) (77A)   ;(011101110101) (3565) (1909) (775)   ;(011101110001) (3561) (1905) (771)   ;(011101101100) (3554) (1900) (76C)   ;(011101100111) (3547) (1895) (767)   ;
;320;(011101100011) (3543) (1891) (763)    ;(011101011110) (3536) (1886) (75E)   ;(011101011001) (3531) (1881) (759)   ;(011101010100) (3524) (1876) (754)   ;(011101001111) (3517) (1871) (74F)   ;(011101001010) (3512) (1866) (74A)   ;(011101000101) (3505) (1861) (745)   ;(011100111111) (3477) (1855) (73F)   ;
;328;(011100111010) (3472) (1850) (73A)    ;(011100110101) (3465) (1845) (735)   ;(011100101111) (3457) (1839) (72F)   ;(011100101010) (3452) (1834) (72A)   ;(011100100100) (3444) (1828) (724)   ;(011100011110) (3436) (1822) (71E)   ;(011100011000) (3430) (1816) (718)   ;(011100010011) (3423) (1811) (713)   ;
;336;(011100001101) (3415) (1805) (70D)    ;(011100000111) (3407) (1799) (707)   ;(011100000001) (3401) (1793) (701)   ;(011011111011) (3373) (1787) (6FB)   ;(011011110101) (3365) (1781) (6F5)   ;(011011101110) (3356) (1774) (6EE)   ;(011011101000) (3350) (1768) (6E8)   ;(011011100010) (3342) (1762) (6E2)   ;
;344;(011011011011) (3333) (1755) (6DB)    ;(011011010101) (3325) (1749) (6D5)   ;(011011001110) (3316) (1742) (6CE)   ;(011011001000) (3310) (1736) (6C8)   ;(011011000001) (3301) (1729) (6C1)   ;(011010111010) (3272) (1722) (6BA)   ;(011010110011) (3263) (1715) (6B3)   ;(011010101100) (3254) (1708) (6AC)   ;
;352;(011010100110) (3246) (1702) (6A6)    ;(011010011111) (3237) (1695) (69F)   ;(011010010111) (3227) (1687) (697)   ;(011010010000) (3220) (1680) (690)   ;(011010001001) (3211) (1673) (689)   ;(011010000010) (3202) (1666) (682)   ;(011001111011) (3173) (1659) (67B)   ;(011001110011) (3163) (1651) (673)   ;
;360;(011001101100) (3154) (1644) (66C)    ;(011001100100) (3144) (1636) (664)   ;(011001011101) (3135) (1629) (65D)   ;(011001010101) (3125) (1621) (655)   ;(011001001101) (3115) (1613) (64D)   ;(011001000101) (3105) (1605) (645)   ;(011000111110) (3076) (1598) (63E)   ;(011000110110) (3066) (1590) (636)   ;
;368;(011000101110) (3056) (1582) (62E)    ;(011000100110) (3046) (1574) (626)   ;(011000011110) (3036) (1566) (61E)   ;(011000010110) (3026) (1558) (616)   ;(011000001110) (3016) (1550) (60E)   ;(011000000101) (3005) (1541) (605)   ;(010111111101) (2775) (1533) (5FD)   ;(010111110101) (2765) (1525) (5F5)   ;
;376;(010111101100) (2754) (1516) (5EC)    ;(010111100100) (2744) (1508) (5E4)   ;(010111011011) (2733) (1499) (5DB)   ;(010111010011) (2723) (1491) (5D3)   ;(010111001010) (2712) (1482) (5CA)   ;(010111000001) (2701) (1473) (5C1)   ;(010110111001) (2671) (1465) (5B9)   ;(010110110000) (2660) (1456) (5B0)   ;
;384;(010110100111) (2647) (1447) (5A7)    ;(010110011110) (2636) (1438) (59E)   ;(010110010101) (2625) (1429) (595)   ;(010110001100) (2614) (1420) (58C)   ;(010110000011) (2603) (1411) (583)   ;(010101111010) (2572) (1402) (57A)   ;(010101110001) (2561) (1393) (571)   ;(010101100111) (2547) (1383) (567)   ;
;392;(010101011110) (2536) (1374) (55E)    ;(010101010101) (2525) (1365) (555)   ;(010101001011) (2513) (1355) (54B)   ;(010101000010) (2502) (1346) (542)   ;(010100111001) (2471) (1337) (539)   ;(010100101111) (2457) (1327) (52F)   ;(010100100101) (2445) (1317) (525)   ;(010100011100) (2434) (1308) (51C)   ;
;400;(010100010010) (2422) (1298) (512)    ;(010100001000) (2410) (1288) (508)   ;(010011111111) (2377) (1279) (4FF)   ;(010011110101) (2365) (1269) (4F5)   ;(010011101011) (2353) (1259) (4EB)   ;(010011100001) (2341) (1249) (4E1)   ;(010011010111) (2327) (1239) (4D7)   ;(010011001101) (2315) (1229) (4CD)   ;
;408;(010011000011) (2303) (1219) (4C3)    ;(010010111001) (2271) (1209) (4B9)   ;(010010101111) (2257) (1199) (4AF)   ;(010010100100) (2244) (1188) (4A4)   ;(010010011010) (2232) (1178) (49A)   ;(010010010000) (2220) (1168) (490)   ;(010010000110) (2206) (1158) (486)   ;(010001111011) (2173) (1147) (47B)   ;
;416;(010001110001) (2161) (1137) (471)    ;(010001100110) (2146) (1126) (466)   ;(010001011100) (2134) (1116) (45C)   ;(010001010001) (2121) (1105) (451)   ;(010001000111) (2107) (1095) (447)   ;(010000111100) (2074) (1084) (43C)   ;(010000110001) (2061) (1073) (431)   ;(010000100111) (2047) (1063) (427)   ;
;424;(010000011100) (2034) (1052) (41C)    ;(010000010001) (2021) (1041) (411)   ;(010000000110) (2006) (1030) (406)   ;(001111111011) (1773) (1019) (3FB)   ;(001111110000) (1760) (1008) (3F0)   ;(001111100110) (1746) (998) (3E6)   ;(001111011011) (1733) (987) (3DB)   ;(001111010000) (1720) (976) (3D0)   ;
;432;(001111000100) (1704) (964) (3C4)    ;(001110111001) (1671) (953) (3B9)   ;(001110101110) (1656) (942) (3AE)   ;(001110100011) (1643) (931) (3A3)   ;(001110011000) (1630) (920) (398)   ;(001110001101) (1615) (909) (38D)   ;(001110000001) (1601) (897) (381)   ;(001101110110) (1566) (886) (376)   ;
;440;(001101101011) (1553) (875) (36B)    ;(001101011111) (1537) (863) (35F)   ;(001101010100) (1524) (852) (354)   ;(001101001000) (1510) (840) (348)   ;(001100111101) (1475) (829) (33D)   ;(001100110010) (1462) (818) (332)   ;(001100100110) (1446) (806) (326)   ;(001100011010) (1432) (794) (31A)   ;
;448;(001100001111) (1417) (783) (30F)    ;(001100000011) (1403) (771) (303)   ;(001011111000) (1370) (760) (2F8)   ;(001011101100) (1354) (748) (2EC)   ;(001011100000) (1340) (736) (2E0)   ;(001011010100) (1324) (724) (2D4)   ;(001011001001) (1311) (713) (2C9)   ;(001010111101) (1275) (701) (2BD)   ;
;456;(001010110001) (1261) (689) (2B1)    ;(001010100101) (1245) (677) (2A5)   ;(001010011001) (1231) (665) (299)   ;(001010001110) (1216) (654) (28E)   ;(001010000010) (1202) (642) (282)   ;(001001110110) (1166) (630) (276)   ;(001001101010) (1152) (618) (26A)   ;(001001011110) (1136) (606) (25E)   ;
;464;(001001010010) (1122) (594) (252)    ;(001001000110) (1106) (582) (246)   ;(001000111010) (1072) (570) (23A)   ;(001000101110) (1056) (558) (22E)   ;(001000100001) (1041) (545) (221)   ;(001000010101) (1025) (533) (215)   ;(001000001001) (1011) (521) (209)   ;(000111111101) (775) (509) (1FD)   ;
;472;(000111110001) (761) (497) (1F1)    ;(000111100101) (745) (485) (1E5)   ;(000111011000) (730) (472) (1D8)   ;(000111001100) (714) (460) (1CC)   ;(000111000000) (700) (448) (1C0)   ;(000110110100) (664) (436) (1B4)   ;(000110100111) (647) (423) (1A7)   ;(000110011011) (633) (411) (19B)   ;
;480;(000110001111) (617) (399) (18F)    ;(000110000011) (603) (387) (183)   ;(000101110110) (566) (374) (176)   ;(000101101010) (552) (362) (16A)   ;(000101011101) (535) (349) (15D)   ;(000101010001) (521) (337) (151)   ;(000101000101) (505) (325) (145)   ;(000100111000) (470) (312) (138)   ;
;488;(000100101100) (454) (300) (12C)    ;(000100011111) (437) (287) (11F)   ;(000100010011) (423) (275) (113)   ;(000100000111) (407) (263) (107)   ;(000011111010) (372) (250) (FA)   ;(000011101110) (356) (238) (EE)   ;(000011100001) (341) (225) (E1)   ;(000011010101) (325) (213) (D5)   ;
;496;(000011001000) (310) (200) (C8)    ;(000010111100) (274) (188) (BC)   ;(000010101111) (257) (175) (AF)   ;(000010100011) (243) (163) (A3)   ;(000010010110) (226) (150) (96)   ;(000010001010) (212) (138) (8A)   ;(000001111101) (175) (125) (7D)   ;(000001110000) (160) (112) (70)   ;
;504;(000001100100) (144) (100) (64)    ;(000001010111) (127) (87) (57)   ;(000001001011) (113) (75) (4B)   ;(000000111110) (76) (62) (3E)   ;(000000110010) (62) (50) (32)   ;(000000100101) (45) (37) (25)   ;(000000011001) (31) (25) (19)   ;(000000001100) (14) (12) (0C)   ;
;512;(000000000000) (0) (0) (00)    ;(111111110100) (7764) (4084) (FF4)   ;(111111100111) (7747) (4071) (FE7)   ;(111111011011) (7733) (4059) (FDB)   ;(111111001110) (7716) (4046) (FCE)   ;(111111000010) (7702) (4034) (FC2)   ;(111110110101) (7665) (4021) (FB5)   ;(111110101001) (7651) (4009) (FA9)   ;
;520;(111110011100) (7634) (3996) (F9C)    ;(111110010000) (7620) (3984) (F90)   ;(111110000011) (7603) (3971) (F83)   ;(111101110110) (7566) (3958) (F76)   ;(111101101010) (7552) (3946) (F6A)   ;(111101011101) (7535) (3933) (F5D)   ;(111101010001) (7521) (3921) (F51)   ;(111101000100) (7504) (3908) (F44)   ;
;528;(111100111000) (7470) (3896) (F38)    ;(111100101011) (7453) (3883) (F2B)   ;(111100011111) (7437) (3871) (F1F)   ;(111100010010) (7422) (3858) (F12)   ;(111100000110) (7406) (3846) (F06)   ;(111011111001) (7371) (3833) (EF9)   ;(111011101101) (7355) (3821) (EED)   ;(111011100001) (7341) (3809) (EE1)   ;
;536;(111011010100) (7324) (3796) (ED4)    ;(111011001000) (7310) (3784) (EC8)   ;(111010111011) (7273) (3771) (EBB)   ;(111010101111) (7257) (3759) (EAF)   ;(111010100011) (7243) (3747) (EA3)   ;(111010010110) (7226) (3734) (E96)   ;(111010001010) (7212) (3722) (E8A)   ;(111001111101) (7175) (3709) (E7D)   ;
;544;(111001110001) (7161) (3697) (E71)    ;(111001100101) (7145) (3685) (E65)   ;(111001011001) (7131) (3673) (E59)   ;(111001001100) (7114) (3660) (E4C)   ;(111001000000) (7100) (3648) (E40)   ;(111000110100) (7064) (3636) (E34)   ;(111000101000) (7050) (3624) (E28)   ;(111000011011) (7033) (3611) (E1B)   ;
;552;(111000001111) (7017) (3599) (E0F)    ;(111000000011) (7003) (3587) (E03)   ;(110111110111) (6767) (3575) (DF7)   ;(110111101011) (6753) (3563) (DEB)   ;(110111011111) (6737) (3551) (DDF)   ;(110111010010) (6722) (3538) (DD2)   ;(110111000110) (6706) (3526) (DC6)   ;(110110111010) (6672) (3514) (DBA)   ;
;560;(110110101110) (6656) (3502) (DAE)    ;(110110100010) (6642) (3490) (DA2)   ;(110110010110) (6626) (3478) (D96)   ;(110110001010) (6612) (3466) (D8A)   ;(110101111110) (6576) (3454) (D7E)   ;(110101110010) (6562) (3442) (D72)   ;(110101100111) (6547) (3431) (D67)   ;(110101011011) (6533) (3419) (D5B)   ;
;568;(110101001111) (6517) (3407) (D4F)    ;(110101000011) (6503) (3395) (D43)   ;(110100110111) (6467) (3383) (D37)   ;(110100101100) (6454) (3372) (D2C)   ;(110100100000) (6440) (3360) (D20)   ;(110100010100) (6424) (3348) (D14)   ;(110100001000) (6410) (3336) (D08)   ;(110011111101) (6375) (3325) (CFD)   ;
;576;(110011110001) (6361) (3313) (CF1)    ;(110011100110) (6346) (3302) (CE6)   ;(110011011010) (6332) (3290) (CDA)   ;(110011001110) (6316) (3278) (CCE)   ;(110011000011) (6303) (3267) (CC3)   ;(110010111000) (6270) (3256) (CB8)   ;(110010101100) (6254) (3244) (CAC)   ;(110010100001) (6241) (3233) (CA1)   ;
;584;(110010010101) (6225) (3221) (C95)    ;(110010001010) (6212) (3210) (C8A)   ;(110001111111) (6177) (3199) (C7F)   ;(110001110011) (6163) (3187) (C73)   ;(110001101000) (6150) (3176) (C68)   ;(110001011101) (6135) (3165) (C5D)   ;(110001010010) (6122) (3154) (C52)   ;(110001000111) (6107) (3143) (C47)   ;
;592;(110000111100) (6074) (3132) (C3C)    ;(110000110000) (6060) (3120) (C30)   ;(110000100101) (6045) (3109) (C25)   ;(110000011010) (6032) (3098) (C1A)   ;(110000010000) (6020) (3088) (C10)   ;(110000000101) (6005) (3077) (C05)   ;(101111111010) (5772) (3066) (BFA)   ;(101111101111) (5757) (3055) (BEF)   ;
;600;(101111100100) (5744) (3044) (BE4)    ;(101111011001) (5731) (3033) (BD9)   ;(101111001111) (5717) (3023) (BCF)   ;(101111000100) (5704) (3012) (BC4)   ;(101110111001) (5671) (3001) (BB9)   ;(101110101111) (5657) (2991) (BAF)   ;(101110100100) (5644) (2980) (BA4)   ;(101110011010) (5632) (2970) (B9A)   ;
;608;(101110001111) (5617) (2959) (B8F)    ;(101110000101) (5605) (2949) (B85)   ;(101101111010) (5572) (2938) (B7A)   ;(101101110000) (5560) (2928) (B70)   ;(101101100110) (5546) (2918) (B66)   ;(101101011100) (5534) (2908) (B5C)   ;(101101010001) (5521) (2897) (B51)   ;(101101000111) (5507) (2887) (B47)   ;
;616;(101100111101) (5475) (2877) (B3D)    ;(101100110011) (5463) (2867) (B33)   ;(101100101001) (5451) (2857) (B29)   ;(101100011111) (5437) (2847) (B1F)   ;(101100010101) (5425) (2837) (B15)   ;(101100001011) (5413) (2827) (B0B)   ;(101100000001) (5401) (2817) (B01)   ;(101011111000) (5370) (2808) (AF8)   ;
;624;(101011101110) (5356) (2798) (AEE)    ;(101011100100) (5344) (2788) (AE4)   ;(101011011011) (5333) (2779) (ADB)   ;(101011010001) (5321) (2769) (AD1)   ;(101011000111) (5307) (2759) (AC7)   ;(101010111110) (5276) (2750) (ABE)   ;(101010110101) (5265) (2741) (AB5)   ;(101010101011) (5253) (2731) (AAB)   ;
;632;(101010100010) (5242) (2722) (AA2)    ;(101010011001) (5231) (2713) (A99)   ;(101010001111) (5217) (2703) (A8F)   ;(101010000110) (5206) (2694) (A86)   ;(101001111101) (5175) (2685) (A7D)   ;(101001110100) (5164) (2676) (A74)   ;(101001101011) (5153) (2667) (A6B)   ;(101001100010) (5142) (2658) (A62)   ;
;640;(101001011001) (5131) (2649) (A59)    ;(101001010000) (5120) (2640) (A50)   ;(101001000111) (5107) (2631) (A47)   ;(101000111111) (5077) (2623) (A3F)   ;(101000110110) (5066) (2614) (A36)   ;(101000101101) (5055) (2605) (A2D)   ;(101000100101) (5045) (2597) (A25)   ;(101000011100) (5034) (2588) (A1C)   ;
;648;(101000010100) (5024) (2580) (A14)    ;(101000001011) (5013) (2571) (A0B)   ;(101000000011) (5003) (2563) (A03)   ;(100111111011) (4773) (2555) (9FB)   ;(100111110010) (4762) (2546) (9F2)   ;(100111101010) (4752) (2538) (9EA)   ;(100111100010) (4742) (2530) (9E2)   ;(100111011010) (4732) (2522) (9DA)   ;
;656;(100111010010) (4722) (2514) (9D2)    ;(100111001010) (4712) (2506) (9CA)   ;(100111000010) (4702) (2498) (9C2)   ;(100110111011) (4673) (2491) (9BB)   ;(100110110011) (4663) (2483) (9B3)   ;(100110101011) (4653) (2475) (9AB)   ;(100110100011) (4643) (2467) (9A3)   ;(100110011100) (4634) (2460) (99C)   ;
;664;(100110010100) (4624) (2452) (994)    ;(100110001101) (4615) (2445) (98D)   ;(100110000101) (4605) (2437) (985)   ;(100101111110) (4576) (2430) (97E)   ;(100101110111) (4567) (2423) (977)   ;(100101110000) (4560) (2416) (970)   ;(100101101001) (4551) (2409) (969)   ;(100101100001) (4541) (2401) (961)   ;
;672;(100101011010) (4532) (2394) (95A)    ;(100101010100) (4524) (2388) (954)   ;(100101001101) (4515) (2381) (94D)   ;(100101000110) (4506) (2374) (946)   ;(100100111111) (4477) (2367) (93F)   ;(100100111000) (4470) (2360) (938)   ;(100100110010) (4462) (2354) (932)   ;(100100101011) (4453) (2347) (92B)   ;
;680;(100100100101) (4445) (2341) (925)    ;(100100011110) (4436) (2334) (91E)   ;(100100011000) (4430) (2328) (918)   ;(100100010010) (4422) (2322) (912)   ;(100100001011) (4413) (2315) (90B)   ;(100100000101) (4405) (2309) (905)   ;(100011111111) (4377) (2303) (8FF)   ;(100011111001) (4371) (2297) (8F9)   ;
;688;(100011110011) (4363) (2291) (8F3)    ;(100011101101) (4355) (2285) (8ED)   ;(100011101000) (4350) (2280) (8E8)   ;(100011100010) (4342) (2274) (8E2)   ;(100011011100) (4334) (2268) (8DC)   ;(100011010110) (4326) (2262) (8D6)   ;(100011010001) (4321) (2257) (8D1)   ;(100011001011) (4313) (2251) (8CB)   ;
;696;(100011000110) (4306) (2246) (8C6)    ;(100011000001) (4301) (2241) (8C1)   ;(100010111011) (4273) (2235) (8BB)   ;(100010110110) (4266) (2230) (8B6)   ;(100010110001) (4261) (2225) (8B1)   ;(100010101100) (4254) (2220) (8AC)   ;(100010100111) (4247) (2215) (8A7)   ;(100010100010) (4242) (2210) (8A2)   ;
;704;(100010011101) (4235) (2205) (89D)    ;(100010011001) (4231) (2201) (899)   ;(100010010100) (4224) (2196) (894)   ;(100010001111) (4217) (2191) (88F)   ;(100010001011) (4213) (2187) (88B)   ;(100010000110) (4206) (2182) (886)   ;(100010000010) (4202) (2178) (882)   ;(100001111101) (4175) (2173) (87D)   ;
;712;(100001111001) (4171) (2169) (879)    ;(100001110101) (4165) (2165) (875)   ;(100001110001) (4161) (2161) (871)   ;(100001101101) (4155) (2157) (86D)   ;(100001101001) (4151) (2153) (869)   ;(100001100101) (4145) (2149) (865)   ;(100001100001) (4141) (2145) (861)   ;(100001011101) (4135) (2141) (85D)   ;
;720;(100001011010) (4132) (2138) (85A)    ;(100001010110) (4126) (2134) (856)   ;(100001010010) (4122) (2130) (852)   ;(100001001111) (4117) (2127) (84F)   ;(100001001100) (4114) (2124) (84C)   ;(100001001000) (4110) (2120) (848)   ;(100001000101) (4105) (2117) (845)   ;(100001000010) (4102) (2114) (842)   ;
;728;(100000111111) (4077) (2111) (83F)    ;(100000111100) (4074) (2108) (83C)   ;(100000111001) (4071) (2105) (839)   ;(100000110110) (4066) (2102) (836)   ;(100000110011) (4063) (2099) (833)   ;(100000110001) (4061) (2097) (831)   ;(100000101110) (4056) (2094) (82E)   ;(100000101011) (4053) (2091) (82B)   ;
;736;(100000101001) (4051) (2089) (829)    ;(100000100110) (4046) (2086) (826)   ;(100000100100) (4044) (2084) (824)   ;(100000100010) (4042) (2082) (822)   ;(100000100000) (4040) (2080) (820)   ;(100000011110) (4036) (2078) (81E)   ;(100000011011) (4033) (2075) (81B)   ;(100000011010) (4032) (2074) (81A)   ;
;744;(100000011000) (4030) (2072) (818)    ;(100000010110) (4026) (2070) (816)   ;(100000010100) (4024) (2068) (814)   ;(100000010010) (4022) (2066) (812)   ;(100000010001) (4021) (2065) (811)   ;(100000001111) (4017) (2063) (80F)   ;(100000001110) (4016) (2062) (80E)   ;(100000001101) (4015) (2061) (80D)   ;
;752;(100000001011) (4013) (2059) (80B)    ;(100000001010) (4012) (2058) (80A)   ;(100000001001) (4011) (2057) (809)   ;(100000001000) (4010) (2056) (808)   ;(100000000111) (4007) (2055) (807)   ;(100000000110) (4006) (2054) (806)   ;(100000000101) (4005) (2053) (805)   ;(100000000101) (4005) (2053) (805)   ;
;760;(100000000100) (4004) (2052) (804)    ;(100000000011) (4003) (2051) (803)   ;(100000000011) (4003) (2051) (803)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;
;768;(100000000001) (4001) (2049) (801)    ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000010) (4002) (2050) (802)   ;(100000000011) (4003) (2051) (803)   ;(100000000011) (4003) (2051) (803)   ;
;776;(100000000100) (4004) (2052) (804)    ;(100000000101) (4005) (2053) (805)   ;(100000000101) (4005) (2053) (805)   ;(100000000110) (4006) (2054) (806)   ;(100000000111) (4007) (2055) (807)   ;(100000001000) (4010) (2056) (808)   ;(100000001001) (4011) (2057) (809)   ;(100000001010) (4012) (2058) (80A)   ;
;784;(100000001011) (4013) (2059) (80B)    ;(100000001101) (4015) (2061) (80D)   ;(100000001110) (4016) (2062) (80E)   ;(100000001111) (4017) (2063) (80F)   ;(100000010001) (4021) (2065) (811)   ;(100000010010) (4022) (2066) (812)   ;(100000010100) (4024) (2068) (814)   ;(100000010110) (4026) (2070) (816)   ;
;792;(100000011000) (4030) (2072) (818)    ;(100000011010) (4032) (2074) (81A)   ;(100000011011) (4033) (2075) (81B)   ;(100000011110) (4036) (2078) (81E)   ;(100000100000) (4040) (2080) (820)   ;(100000100010) (4042) (2082) (822)   ;(100000100100) (4044) (2084) (824)   ;(100000100110) (4046) (2086) (826)   ;
;800;(100000101001) (4051) (2089) (829)    ;(100000101011) (4053) (2091) (82B)   ;(100000101110) (4056) (2094) (82E)   ;(100000110001) (4061) (2097) (831)   ;(100000110011) (4063) (2099) (833)   ;(100000110110) (4066) (2102) (836)   ;(100000111001) (4071) (2105) (839)   ;(100000111100) (4074) (2108) (83C)   ;
;808;(100000111111) (4077) (2111) (83F)    ;(100001000010) (4102) (2114) (842)   ;(100001000101) (4105) (2117) (845)   ;(100001001000) (4110) (2120) (848)   ;(100001001100) (4114) (2124) (84C)   ;(100001001111) (4117) (2127) (84F)   ;(100001010010) (4122) (2130) (852)   ;(100001010110) (4126) (2134) (856)   ;
;816;(100001011010) (4132) (2138) (85A)    ;(100001011101) (4135) (2141) (85D)   ;(100001100001) (4141) (2145) (861)   ;(100001100101) (4145) (2149) (865)   ;(100001101001) (4151) (2153) (869)   ;(100001101101) (4155) (2157) (86D)   ;(100001110001) (4161) (2161) (871)   ;(100001110101) (4165) (2165) (875)   ;
;824;(100001111001) (4171) (2169) (879)    ;(100001111101) (4175) (2173) (87D)   ;(100010000010) (4202) (2178) (882)   ;(100010000110) (4206) (2182) (886)   ;(100010001011) (4213) (2187) (88B)   ;(100010001111) (4217) (2191) (88F)   ;(100010010100) (4224) (2196) (894)   ;(100010011001) (4231) (2201) (899)   ;
;832;(100010011101) (4235) (2205) (89D)    ;(100010100010) (4242) (2210) (8A2)   ;(100010100111) (4247) (2215) (8A7)   ;(100010101100) (4254) (2220) (8AC)   ;(100010110001) (4261) (2225) (8B1)   ;(100010110110) (4266) (2230) (8B6)   ;(100010111011) (4273) (2235) (8BB)   ;(100011000001) (4301) (2241) (8C1)   ;
;840;(100011000110) (4306) (2246) (8C6)    ;(100011001011) (4313) (2251) (8CB)   ;(100011010001) (4321) (2257) (8D1)   ;(100011010110) (4326) (2262) (8D6)   ;(100011011100) (4334) (2268) (8DC)   ;(100011100010) (4342) (2274) (8E2)   ;(100011101000) (4350) (2280) (8E8)   ;(100011101101) (4355) (2285) (8ED)   ;
;848;(100011110011) (4363) (2291) (8F3)    ;(100011111001) (4371) (2297) (8F9)   ;(100011111111) (4377) (2303) (8FF)   ;(100100000101) (4405) (2309) (905)   ;(100100001011) (4413) (2315) (90B)   ;(100100010010) (4422) (2322) (912)   ;(100100011000) (4430) (2328) (918)   ;(100100011110) (4436) (2334) (91E)   ;
;856;(100100100101) (4445) (2341) (925)    ;(100100101011) (4453) (2347) (92B)   ;(100100110010) (4462) (2354) (932)   ;(100100111000) (4470) (2360) (938)   ;(100100111111) (4477) (2367) (93F)   ;(100101000110) (4506) (2374) (946)   ;(100101001101) (4515) (2381) (94D)   ;(100101010100) (4524) (2388) (954)   ;
;864;(100101011010) (4532) (2394) (95A)    ;(100101100001) (4541) (2401) (961)   ;(100101101001) (4551) (2409) (969)   ;(100101110000) (4560) (2416) (970)   ;(100101110111) (4567) (2423) (977)   ;(100101111110) (4576) (2430) (97E)   ;(100110000101) (4605) (2437) (985)   ;(100110001101) (4615) (2445) (98D)   ;
;872;(100110010100) (4624) (2452) (994)    ;(100110011100) (4634) (2460) (99C)   ;(100110100011) (4643) (2467) (9A3)   ;(100110101011) (4653) (2475) (9AB)   ;(100110110011) (4663) (2483) (9B3)   ;(100110111011) (4673) (2491) (9BB)   ;(100111000010) (4702) (2498) (9C2)   ;(100111001010) (4712) (2506) (9CA)   ;
;880;(100111010010) (4722) (2514) (9D2)    ;(100111011010) (4732) (2522) (9DA)   ;(100111100010) (4742) (2530) (9E2)   ;(100111101010) (4752) (2538) (9EA)   ;(100111110010) (4762) (2546) (9F2)   ;(100111111011) (4773) (2555) (9FB)   ;(101000000011) (5003) (2563) (A03)   ;(101000001011) (5013) (2571) (A0B)   ;
;888;(101000010100) (5024) (2580) (A14)    ;(101000011100) (5034) (2588) (A1C)   ;(101000100101) (5045) (2597) (A25)   ;(101000101101) (5055) (2605) (A2D)   ;(101000110110) (5066) (2614) (A36)   ;(101000111111) (5077) (2623) (A3F)   ;(101001000111) (5107) (2631) (A47)   ;(101001010000) (5120) (2640) (A50)   ;
;896;(101001011001) (5131) (2649) (A59)    ;(101001100010) (5142) (2658) (A62)   ;(101001101011) (5153) (2667) (A6B)   ;(101001110100) (5164) (2676) (A74)   ;(101001111101) (5175) (2685) (A7D)   ;(101010000110) (5206) (2694) (A86)   ;(101010001111) (5217) (2703) (A8F)   ;(101010011001) (5231) (2713) (A99)   ;
;904;(101010100010) (5242) (2722) (AA2)    ;(101010101011) (5253) (2731) (AAB)   ;(101010110101) (5265) (2741) (AB5)   ;(101010111110) (5276) (2750) (ABE)   ;(101011000111) (5307) (2759) (AC7)   ;(101011010001) (5321) (2769) (AD1)   ;(101011011011) (5333) (2779) (ADB)   ;(101011100100) (5344) (2788) (AE4)   ;
;912;(101011101110) (5356) (2798) (AEE)    ;(101011111000) (5370) (2808) (AF8)   ;(101100000001) (5401) (2817) (B01)   ;(101100001011) (5413) (2827) (B0B)   ;(101100010101) (5425) (2837) (B15)   ;(101100011111) (5437) (2847) (B1F)   ;(101100101001) (5451) (2857) (B29)   ;(101100110011) (5463) (2867) (B33)   ;
;920;(101100111101) (5475) (2877) (B3D)    ;(101101000111) (5507) (2887) (B47)   ;(101101010001) (5521) (2897) (B51)   ;(101101011100) (5534) (2908) (B5C)   ;(101101100110) (5546) (2918) (B66)   ;(101101110000) (5560) (2928) (B70)   ;(101101111010) (5572) (2938) (B7A)   ;(101110000101) (5605) (2949) (B85)   ;
;928;(101110001111) (5617) (2959) (B8F)    ;(101110011010) (5632) (2970) (B9A)   ;(101110100100) (5644) (2980) (BA4)   ;(101110101111) (5657) (2991) (BAF)   ;(101110111001) (5671) (3001) (BB9)   ;(101111000100) (5704) (3012) (BC4)   ;(101111001111) (5717) (3023) (BCF)   ;(101111011001) (5731) (3033) (BD9)   ;
;936;(101111100100) (5744) (3044) (BE4)    ;(101111101111) (5757) (3055) (BEF)   ;(101111111010) (5772) (3066) (BFA)   ;(110000000101) (6005) (3077) (C05)   ;(110000010000) (6020) (3088) (C10)   ;(110000011010) (6032) (3098) (C1A)   ;(110000100101) (6045) (3109) (C25)   ;(110000110000) (6060) (3120) (C30)   ;
;944;(110000111100) (6074) (3132) (C3C)    ;(110001000111) (6107) (3143) (C47)   ;(110001010010) (6122) (3154) (C52)   ;(110001011101) (6135) (3165) (C5D)   ;(110001101000) (6150) (3176) (C68)   ;(110001110011) (6163) (3187) (C73)   ;(110001111111) (6177) (3199) (C7F)   ;(110010001010) (6212) (3210) (C8A)   ;
;952;(110010010101) (6225) (3221) (C95)    ;(110010100001) (6241) (3233) (CA1)   ;(110010101100) (6254) (3244) (CAC)   ;(110010111000) (6270) (3256) (CB8)   ;(110011000011) (6303) (3267) (CC3)   ;(110011001110) (6316) (3278) (CCE)   ;(110011011010) (6332) (3290) (CDA)   ;(110011100110) (6346) (3302) (CE6)   ;
;960;(110011110001) (6361) (3313) (CF1)    ;(110011111101) (6375) (3325) (CFD)   ;(110100001000) (6410) (3336) (D08)   ;(110100010100) (6424) (3348) (D14)   ;(110100100000) (6440) (3360) (D20)   ;(110100101100) (6454) (3372) (D2C)   ;(110100110111) (6467) (3383) (D37)   ;(110101000011) (6503) (3395) (D43)   ;
;968;(110101001111) (6517) (3407) (D4F)    ;(110101011011) (6533) (3419) (D5B)   ;(110101100111) (6547) (3431) (D67)   ;(110101110010) (6562) (3442) (D72)   ;(110101111110) (6576) (3454) (D7E)   ;(110110001010) (6612) (3466) (D8A)   ;(110110010110) (6626) (3478) (D96)   ;(110110100010) (6642) (3490) (DA2)   ;
;976;(110110101110) (6656) (3502) (DAE)    ;(110110111010) (6672) (3514) (DBA)   ;(110111000110) (6706) (3526) (DC6)   ;(110111010010) (6722) (3538) (DD2)   ;(110111011111) (6737) (3551) (DDF)   ;(110111101011) (6753) (3563) (DEB)   ;(110111110111) (6767) (3575) (DF7)   ;(111000000011) (7003) (3587) (E03)   ;
;984;(111000001111) (7017) (3599) (E0F)    ;(111000011011) (7033) (3611) (E1B)   ;(111000101000) (7050) (3624) (E28)   ;(111000110100) (7064) (3636) (E34)   ;(111001000000) (7100) (3648) (E40)   ;(111001001100) (7114) (3660) (E4C)   ;(111001011001) (7131) (3673) (E59)   ;(111001100101) (7145) (3685) (E65)   ;
;992;(111001110001) (7161) (3697) (E71)    ;(111001111101) (7175) (3709) (E7D)   ;(111010001010) (7212) (3722) (E8A)   ;(111010010110) (7226) (3734) (E96)   ;(111010100011) (7243) (3747) (EA3)   ;(111010101111) (7257) (3759) (EAF)   ;(111010111011) (7273) (3771) (EBB)   ;(111011001000) (7310) (3784) (EC8)   ;
;1000;(111011010100) (7324) (3796) (ED4)    ;(111011100001) (7341) (3809) (EE1)   ;(111011101101) (7355) (3821) (EED)   ;(111011111001) (7371) (3833) (EF9)   ;(111100000110) (7406) (3846) (F06)   ;(111100010010) (7422) (3858) (F12)   ;(111100011111) (7437) (3871) (F1F)   ;(111100101011) (7453) (3883) (F2B)   ;
;1008;(111100111000) (7470) (3896) (F38)    ;(111101000100) (7504) (3908) (F44)   ;(111101010001) (7521) (3921) (F51)   ;(111101011101) (7535) (3933) (F5D)   ;(111101101010) (7552) (3946) (F6A)   ;(111101110110) (7566) (3958) (F76)   ;(111110000011) (7603) (3971) (F83)   ;(111110010000) (7620) (3984) (F90)   ;
;1016;(111110011100) (7634) (3996) (F9C)    ;(111110101001) (7651) (4009) (FA9)   ;(111110110101) (7665) (4021) (FB5)   ;(111111000010) (7702) (4034) (FC2)   ;(111111001110) (7716) (4046) (FCE)   ;(111111011011) (7733) (4059) (FDB)   ;(111111100111) (7747) (4071) (FE7)   ;(111111110100) (7764) (4084) (FF4)   ;


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 1,872 / 47,787 ( 4 % ) ;
; C16 interconnects     ; 15 / 1,804 ( < 1 % )   ;
; C4 interconnects      ; 850 / 31,272 ( 3 % )   ;
; Direct links          ; 424 / 47,787 ( < 1 % ) ;
; Global clocks         ; 4 / 20 ( 20 % )        ;
; Local interconnects   ; 944 / 15,408 ( 6 % )   ;
; R24 interconnects     ; 18 / 1,775 ( 1 % )     ;
; R4 interconnects      ; 918 / 41,310 ( 2 % )   ;
+-----------------------+------------------------+


+-----------------------------------------------------------------------------+
; LAB Logic Elements                                                          ;
+---------------------------------------------+-------------------------------+
; Number of Logic Elements  (Average = 12.66) ; Number of LABs  (Total = 119) ;
+---------------------------------------------+-------------------------------+
; 1                                           ; 6                             ;
; 2                                           ; 2                             ;
; 3                                           ; 6                             ;
; 4                                           ; 0                             ;
; 5                                           ; 1                             ;
; 6                                           ; 3                             ;
; 7                                           ; 2                             ;
; 8                                           ; 1                             ;
; 9                                           ; 1                             ;
; 10                                          ; 4                             ;
; 11                                          ; 8                             ;
; 12                                          ; 5                             ;
; 13                                          ; 4                             ;
; 14                                          ; 10                            ;
; 15                                          ; 11                            ;
; 16                                          ; 55                            ;
+---------------------------------------------+-------------------------------+


+--------------------------------------------------------------------+
; LAB-wide Signals                                                   ;
+------------------------------------+-------------------------------+
; LAB-wide Signals  (Average = 1.93) ; Number of LABs  (Total = 119) ;
+------------------------------------+-------------------------------+
; 1 Async. clear                     ; 55                            ;
; 1 Clock                            ; 85                            ;
; 1 Clock enable                     ; 43                            ;
; 1 Sync. clear                      ; 9                             ;
; 1 Sync. load                       ; 4                             ;
; 2 Clock enables                    ; 12                            ;
; 2 Clocks                           ; 22                            ;
+------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Signals Sourced                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Signals Sourced  (Average = 21.13) ; Number of LABs  (Total = 119) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 2                             ;
; 1                                            ; 1                             ;
; 2                                            ; 4                             ;
; 3                                            ; 1                             ;
; 4                                            ; 2                             ;
; 5                                            ; 1                             ;
; 6                                            ; 3                             ;
; 7                                            ; 0                             ;
; 8                                            ; 0                             ;
; 9                                            ; 0                             ;
; 10                                           ; 2                             ;
; 11                                           ; 1                             ;
; 12                                           ; 2                             ;
; 13                                           ; 0                             ;
; 14                                           ; 3                             ;
; 15                                           ; 0                             ;
; 16                                           ; 10                            ;
; 17                                           ; 1                             ;
; 18                                           ; 3                             ;
; 19                                           ; 3                             ;
; 20                                           ; 5                             ;
; 21                                           ; 7                             ;
; 22                                           ; 3                             ;
; 23                                           ; 8                             ;
; 24                                           ; 6                             ;
; 25                                           ; 10                            ;
; 26                                           ; 7                             ;
; 27                                           ; 2                             ;
; 28                                           ; 7                             ;
; 29                                           ; 8                             ;
; 30                                           ; 5                             ;
; 31                                           ; 3                             ;
; 32                                           ; 9                             ;
+----------------------------------------------+-------------------------------+


+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                         ;
+-------------------------------------------------+-------------------------------+
; Number of Signals Sourced Out  (Average = 6.41) ; Number of LABs  (Total = 119) ;
+-------------------------------------------------+-------------------------------+
; 0                                               ; 3                             ;
; 1                                               ; 21                            ;
; 2                                               ; 16                            ;
; 3                                               ; 20                            ;
; 4                                               ; 9                             ;
; 5                                               ; 4                             ;
; 6                                               ; 1                             ;
; 7                                               ; 2                             ;
; 8                                               ; 3                             ;
; 9                                               ; 2                             ;
; 10                                              ; 5                             ;
; 11                                              ; 7                             ;
; 12                                              ; 3                             ;
; 13                                              ; 3                             ;
; 14                                              ; 3                             ;
; 15                                              ; 3                             ;
; 16                                              ; 12                            ;
; 17                                              ; 0                             ;
; 18                                              ; 0                             ;
; 19                                              ; 0                             ;
; 20                                              ; 0                             ;
; 21                                              ; 0                             ;
; 22                                              ; 1                             ;
; 23                                              ; 0                             ;
; 24                                              ; 0                             ;
; 25                                              ; 0                             ;
; 26                                              ; 0                             ;
; 27                                              ; 0                             ;
; 28                                              ; 0                             ;
; 29                                              ; 1                             ;
+-------------------------------------------------+-------------------------------+


+------------------------------------------------------------------------------+
; LAB Distinct Inputs                                                          ;
+----------------------------------------------+-------------------------------+
; Number of Distinct Inputs  (Average = 10.43) ; Number of LABs  (Total = 119) ;
+----------------------------------------------+-------------------------------+
; 0                                            ; 0                             ;
; 1                                            ; 1                             ;
; 2                                            ; 7                             ;
; 3                                            ; 19                            ;
; 4                                            ; 5                             ;
; 5                                            ; 6                             ;
; 6                                            ; 3                             ;
; 7                                            ; 9                             ;
; 8                                            ; 3                             ;
; 9                                            ; 10                            ;
; 10                                           ; 4                             ;
; 11                                           ; 5                             ;
; 12                                           ; 5                             ;
; 13                                           ; 1                             ;
; 14                                           ; 2                             ;
; 15                                           ; 3                             ;
; 16                                           ; 5                             ;
; 17                                           ; 7                             ;
; 18                                           ; 2                             ;
; 19                                           ; 3                             ;
; 20                                           ; 4                             ;
; 21                                           ; 4                             ;
; 22                                           ; 5                             ;
; 23                                           ; 0                             ;
; 24                                           ; 0                             ;
; 25                                           ; 1                             ;
; 26                                           ; 1                             ;
; 27                                           ; 0                             ;
; 28                                           ; 0                             ;
; 29                                           ; 0                             ;
; 30                                           ; 0                             ;
; 31                                           ; 0                             ;
; 32                                           ; 1                             ;
; 33                                           ; 0                             ;
; 34                                           ; 1                             ;
+----------------------------------------------+-------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 12    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 18    ;
+----------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules           ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass          ; 4            ; 0            ; 4            ; 0            ; 0            ; 21        ; 4            ; 0            ; 21        ; 21        ; 0            ; 13           ; 0            ; 0            ; 4            ; 0            ; 13           ; 4            ; 0            ; 0            ; 0            ; 13           ; 0            ; 0            ; 0            ; 0            ; 0            ; 21        ; 0            ; 0            ;
; Total Unchecked     ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable  ; 17           ; 21           ; 17           ; 21           ; 21           ; 0         ; 17           ; 21           ; 0         ; 0         ; 21           ; 8            ; 21           ; 21           ; 17           ; 21           ; 8            ; 17           ; 21           ; 21           ; 21           ; 8            ; 21           ; 21           ; 21           ; 21           ; 21           ; 0         ; 21           ; 21           ;
; Total Fail          ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; CLKOUT              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[1]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[2]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[3]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[4]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[5]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[6]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[7]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[8]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[9]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[10]          ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SINOUT[11]          ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; CLK                 ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; BUTRST              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; BUTUP               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; BUTDOWN             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+---------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                       ;
+------------------------------------------------------------------+--------------------------+
; Option                                                           ; Setting                  ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
; Enable INIT_DONE output                                          ; Off                      ;
; Configuration scheme                                             ; Active Serial            ;
; Error detection CRC                                              ; Off                      ;
; Enable open drain on CRC_ERROR pin                               ; Off                      ;
; Enable input tri-state on active configuration pins in user mode ; Off                      ;
; Configuration Voltage Level                                      ; Auto                     ;
; Force Configuration Voltage Level                                ; Off                      ;
; nCEO                                                             ; As output driving ground ;
; Data[0]                                                          ; As input tri-stated      ;
; Data[1]/ASDO                                                     ; As input tri-stated      ;
; Data[7..2]                                                       ; Unreserved               ;
; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
; Other Active Parallel pins                                       ; Unreserved               ;
; DCLK                                                             ; As output driving ground ;
; Base pin-out file on sameframe device                            ; Off                      ;
+------------------------------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (119006): Selected device EP3C16F484C6 for design "top_sin_wave"
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device EP3C40F484C6 is compatible
    Info (176445): Device EP3C55F484C6 is compatible
    Info (176445): Device EP3C80F484C6 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (169085): No exact pin location assignment(s) for 13 pins of 17 total pins
    Info (169086): Pin CLKOUT not assigned to an exact location on the device
    Info (169086): Pin SINOUT[0] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[1] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[2] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[3] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[4] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[5] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[6] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[7] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[8] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[9] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[10] not assigned to an exact location on the device
    Info (169086): Pin SINOUT[11] not assigned to an exact location on the device
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_jtag_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Critical Warning (332012): Synopsys Design Constraints File file not found: 'top_sin_wave.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332060): Node: CLK was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 1 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):  100.000 altera_reserved_tck
Info (176353): Automatically promoted node CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node CLKOUT~output
Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset
Info (176353): Automatically promoted node rst_W 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176218): Packed 12 registers into blocks of type EC
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info (176211): Number of I/O pins in group: 13 (unused VREF, 2.5V VCCIO, 0 input, 13 output, 0 bidirectional)
        Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
    Info (176214): Statistics of I/O banks
        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 11 total pin(s) used --  26 pins available
        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  41 pins available
        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 2% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 9% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 0.62 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
Info (144001): Generated suppressed messages file D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 1125 megabytes
    Info: Processing ended: Sun Jun 07 20:49:26 2015
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:11


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/top_sin_wave.fit.smsg.


