Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/ --output-directory=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/ --report-file=bsf:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.bsf --system-info=DEVICE_FAMILY="Cyclone III" --system-info=DEVICE=EP3C16F484C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.qsys
Progress: Loading prj_q131/JTAG_MM.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.1]
Progress: Parameterizing module clk_0
Progress: Adding master_0 [altera_jtag_avalon_master 13.1]
Progress: Parameterizing module master_0
Progress: Adding POUT [altera_avalon_pio 13.1]
Progress: Parameterizing module POUT
Progress: Adding PIN [altera_avalon_pio 13.1]
Progress: Parameterizing module PIN
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: JTAG_MM.PIN: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/ --output-directory=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/ --file-set=QUARTUS_SYNTH --report-file=html:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.html --report-file=sopcinfo:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.sopcinfo --report-file=cmp:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.cmp --report-file=qip:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.qip --report-file=svd --report-file=regmap:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.regmap --report-file=debuginfo:D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.debuginfo --system-info=DEVICE_FAMILY="Cyclone III" --system-info=DEVICE=EP3C16F484C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM.qsys --language=VERILOG
Progress: Loading prj_q131/JTAG_MM.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.1]
Progress: Parameterizing module clk_0
Progress: Adding master_0 [altera_jtag_avalon_master 13.1]
Progress: Parameterizing module master_0
Progress: Adding POUT [altera_avalon_pio 13.1]
Progress: Parameterizing module POUT
Progress: Adding PIN [altera_avalon_pio 13.1]
Progress: Parameterizing module PIN
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: JTAG_MM.PIN: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: JTAG_MM: Generating JTAG_MM "JTAG_MM" for QUARTUS_SYNTH
Info: pipeline_bridge_swap_transform: After transform: 4 modules, 8 connections
Info: No custom instruction connections, skipping transform 
Info: merlin_initial_interconnect_transform: After transform: 4 modules, 8 connections
Info: merlin_translator_transform: After transform: 7 modules, 17 connections
Info: merlin_domain_transform: After transform: 13 modules, 46 connections
Info: merlin_router_transform: After transform: 16 modules, 55 connections
Info: merlin_traffic_limiter_transform: After transform: 17 modules, 59 connections
Info: merlin_network_to_switch_transform: After transform: 22 modules, 69 connections
Info: limiter_update_transform: After transform: 22 modules, 70 connections
Info: merlin_clock_and_reset_bridge_transform: After transform: 25 modules, 94 connections
Info: merlin_hierarchy_transform: After transform: 5 modules, 12 connections
Info: merlin_mm_transform: After transform: 5 modules, 12 connections
Info: reset_adaptation_transform: After transform: 6 modules, 14 connections
Info: pipeline_bridge_swap_transform: After transform: 10 modules, 24 connections
Info: No custom instruction connections, skipping transform 
Info: reset_adaptation_transform: After transform: 11 modules, 26 connections
Info: master_0: "JTAG_MM" instantiated altera_jtag_avalon_master "master_0"
Info: POUT: Starting RTL generation for module 'JTAG_MM_POUT'
Info: POUT:   Generation command is [exec C:/altera/13.1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.1/quartus/bin/perl/lib -I C:/altera/13.1/quartus/sopc_builder/bin/europa -I C:/altera/13.1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.1/quartus/sopc_builder/bin -I C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=JTAG_MM_POUT --dir=C:/Users/duweitao/AppData/Local/Temp/alt6594_896363527449734859.dir/0001_POUT_gen/ --quartus_dir=C:/altera/13.1/quartus --verilog --config=C:/Users/duweitao/AppData/Local/Temp/alt6594_896363527449734859.dir/0001_POUT_gen//JTAG_MM_POUT_component_configuration.pl  --do_build_sim=0  ]
Info: POUT: Done RTL generation for module 'JTAG_MM_POUT'
Info: POUT: "JTAG_MM" instantiated altera_avalon_pio "POUT"
Info: PIN: Starting RTL generation for module 'JTAG_MM_PIN'
Info: PIN:   Generation command is [exec C:/altera/13.1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.1/quartus/bin/perl/lib -I C:/altera/13.1/quartus/sopc_builder/bin/europa -I C:/altera/13.1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.1/quartus/sopc_builder/bin -I C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=JTAG_MM_PIN --dir=C:/Users/duweitao/AppData/Local/Temp/alt6594_896363527449734859.dir/0002_PIN_gen/ --quartus_dir=C:/altera/13.1/quartus --verilog --config=C:/Users/duweitao/AppData/Local/Temp/alt6594_896363527449734859.dir/0002_PIN_gen//JTAG_MM_PIN_component_configuration.pl  --do_build_sim=0  ]
Info: PIN: Done RTL generation for module 'JTAG_MM_PIN'
Info: PIN: "JTAG_MM" instantiated altera_avalon_pio "PIN"
Info: pipeline_bridge_swap_transform: After transform: 21 modules, 63 connections
Info: No custom instruction connections, skipping transform 
Info: merlin_initial_interconnect_transform: After transform: 0 modules, 0 connections
Info: No Avalon connections, skipping transform 
Info: merlin_hierarchy_transform: After transform: 21 modules, 63 connections
Info: merlin_initial_interconnect_transform: After transform: 0 modules, 0 connections
Info: No Avalon connections, skipping transform 
Info: merlin_hierarchy_transform: After transform: 21 modules, 63 connections
Info: merlin_initial_interconnect_transform: After transform: 0 modules, 0 connections
Info: No Avalon connections, skipping transform 
Info: merlin_hierarchy_transform: After transform: 21 modules, 63 connections
Info: mm_interconnect_0: "JTAG_MM" instantiated altera_merlin_interconnect_wrapper "mm_interconnect_0"
Info: rst_controller: "JTAG_MM" instantiated altera_reset_controller "rst_controller"
Info: jtag_phy_embedded_in_jtag_master: "master_0" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master"
Info: timing_adt: Starting generation. 
Info: timing_adt: "master_0" instantiated timing_adapter "timing_adt"
Info: fifo: "master_0" instantiated altera_avalon_sc_fifo "fifo"
Info: b2p: "master_0" instantiated altera_avalon_st_bytes_to_packets "b2p"
Info: p2b: "master_0" instantiated altera_avalon_st_packets_to_bytes "p2b"
Info: transacto: "master_0" instantiated altera_avalon_packets_to_master "transacto"
Info: b2p_adapter: Starting generation. 
Info: b2p_adapter: "master_0" instantiated channel_adapter "b2p_adapter"
Info: p2b_adapter: Starting generation. 
Info: p2b_adapter: "master_0" instantiated channel_adapter "p2b_adapter"
Info: master_0_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "master_0_master_translator"
Info: POUT_s1_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "POUT_s1_translator"
Info: master_0_master_translator_avalon_universal_master_0_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "master_0_master_translator_avalon_universal_master_0_agent"
Info: POUT_s1_translator_avalon_universal_slave_0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "POUT_s1_translator_avalon_universal_slave_0_agent"
Info: addr_router: "mm_interconnect_0" instantiated altera_merlin_router "addr_router"
Info: id_router: "mm_interconnect_0" instantiated altera_merlin_router "id_router"
Info: limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "limiter"
Info: Reusing file D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v
Info: Reusing file D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_xbar_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"
Info: cmd_xbar_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_xbar_mux"
Info: rsp_xbar_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_xbar_demux"
Info: rsp_xbar_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_xbar_mux"
Info: Reusing file D:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv
Info: JTAG_MM: Done "JTAG_MM" with 25 modules, 39 files, 499393 bytes
Info: ip-generate succeeded.
Info: Finished: Create HDL design files for synthesis
