{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1433814815132 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1433814815132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 09 09:53:34 2015 " "Processing started: Tue Jun 09 09:53:34 2015" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1433814815132 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1433814815132 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1433814815132 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1433814815482 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/top.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815557 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/jtag_mm.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/jtag_mm.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM " "Found entity 1: JTAG_MM" {  } { { "JTAG_MM/synthesis/JTAG_MM.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815560 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815560 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" {  } { { "JTAG_MM/synthesis/submodules/altera_reset_controller.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815563 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815563 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" {  } { { "JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815565 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815565 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0 " "Found entity 1: JTAG_MM_mm_interconnect_0" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815570 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815570 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815573 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815573 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815573 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_rsp_xbar_mux " "Found entity 1: JTAG_MM_mm_interconnect_0_rsp_xbar_mux" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv" 38 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815575 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815575 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_rsp_xbar_demux " "Found entity 1: JTAG_MM_mm_interconnect_0_rsp_xbar_demux" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_demux.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815577 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815577 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_cmd_xbar_mux " "Found entity 1: JTAG_MM_mm_interconnect_0_cmd_xbar_mux" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_mux.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_mux.sv" 38 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815579 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_cmd_xbar_demux " "Found entity 1: JTAG_MM_mm_interconnect_0_cmd_xbar_demux" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_demux.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815581 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815581 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815585 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815585 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815588 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_reorder_memory.sv" 187 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815588 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815593 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815593 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815595 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815595 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel JTAG_MM_mm_interconnect_0_id_router.sv(48) " "Verilog HDL Declaration information at JTAG_MM_mm_interconnect_0_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1433814815597 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel JTAG_MM_mm_interconnect_0_id_router.sv(49) " "Verilog HDL Declaration information at JTAG_MM_mm_interconnect_0_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1433814815597 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_id_router_default_decode " "Found entity 1: JTAG_MM_mm_interconnect_0_id_router_default_decode" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815597 ""} { "Info" "ISGN_ENTITY_NAME" "2 JTAG_MM_mm_interconnect_0_id_router " "Found entity 2: JTAG_MM_mm_interconnect_0_id_router" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" 86 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815597 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815597 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel JTAG_MM_mm_interconnect_0_addr_router.sv(48) " "Verilog HDL Declaration information at JTAG_MM_mm_interconnect_0_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1433814815599 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel JTAG_MM_mm_interconnect_0_addr_router.sv(49) " "Verilog HDL Declaration information at JTAG_MM_mm_interconnect_0_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1433814815599 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_mm_interconnect_0_addr_router_default_decode " "Found entity 1: JTAG_MM_mm_interconnect_0_addr_router_default_decode" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815600 ""} { "Info" "ISGN_ENTITY_NAME" "2 JTAG_MM_mm_interconnect_0_addr_router " "Found entity 2: JTAG_MM_mm_interconnect_0_addr_router" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" 86 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815600 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815603 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815603 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815605 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815605 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815608 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815608 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815610 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815610 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815613 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815613 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_pin.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_pin.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_PIN " "Found entity 1: JTAG_MM_PIN" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_PIN.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_PIN.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815615 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815615 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_pout.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_pout.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_POUT " "Found entity 1: JTAG_MM_POUT" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_POUT.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_POUT.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815618 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815618 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_master_0.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_master_0 " "Found entity 1: JTAG_MM_master_0" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815620 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815620 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_master_0_p2b_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_p2b_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_master_0_p2b_adapter " "Found entity 1: JTAG_MM_master_0_p2b_adapter" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0_p2b_adapter.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_p2b_adapter.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815622 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815622 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_master_0_b2p_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_b2p_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_master_0_b2p_adapter " "Found entity 1: JTAG_MM_master_0_b2p_adapter" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815624 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815624 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_packets_to_master.v 7 7 " "Found 7 design units, including 7 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_packets_to_master.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_packets_to_master " "Found entity 1: altera_avalon_packets_to_master" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "2 packets_to_fifo " "Found entity 2: packets_to_fifo" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 129 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "3 fifo_buffer_single_clock_fifo " "Found entity 3: fifo_buffer_single_clock_fifo" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 499 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "4 fifo_buffer_scfifo_with_controls " "Found entity 4: fifo_buffer_scfifo_with_controls" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 560 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "5 fifo_buffer " "Found entity 5: fifo_buffer" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 614 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "6 fifo_to_packet " "Found entity 6: fifo_to_packet" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 684 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""} { "Info" "ISGN_ENTITY_NAME" "7 packets_to_master " "Found entity 7: packets_to_master" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 838 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815630 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_packets_to_bytes.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_packets_to_bytes.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_packets_to_bytes " "Found entity 1: altera_avalon_st_packets_to_bytes" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815633 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_bytes_to_packets.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_bytes_to_packets.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_bytes_to_packets " "Found entity 1: altera_avalon_st_bytes_to_packets" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_bytes_to_packets.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_bytes_to_packets.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815637 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815637 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/jtag_mm_master_0_timing_adt.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_timing_adt.v" { { "Info" "ISGN_ENTITY_NAME" "1 JTAG_MM_master_0_timing_adt " "Found entity 1: JTAG_MM_master_0_timing_adt" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0_timing_adt.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_timing_adt.v" 7 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815640 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815640 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_jtag_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_jtag_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_jtag_interface " "Found entity 1: altera_avalon_st_jtag_interface" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v" 7 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815643 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815643 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_jtag_dc_streaming.v 3 3 " "Found 3 design units, including 3 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_dc_streaming.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_jtag_control_signal_crosser " "Found entity 1: altera_jtag_control_signal_crosser" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815645 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_jtag_src_crosser " "Found entity 2: altera_jtag_src_crosser" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 59 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815645 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_jtag_dc_streaming " "Found entity 3: altera_jtag_dc_streaming" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 122 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815645 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815645 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_jtag_sld_node.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_sld_node.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_jtag_sld_node " "Found entity 1: altera_jtag_sld_node" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815648 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815648 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_jtag_streaming.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_streaming.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_jtag_streaming " "Found entity 1: altera_jtag_streaming" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815651 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815651 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_pli_streaming.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_pli_streaming.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_pli_streaming " "Found entity 1: altera_pli_streaming" {  } { { "JTAG_MM/synthesis/submodules/altera_pli_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_pli_streaming.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815653 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815653 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_clock_crosser.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_clock_crosser.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_clock_crosser " "Found entity 1: altera_avalon_st_clock_crosser" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815655 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815655 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_idle_remover.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_idle_remover.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_idle_remover " "Found entity 1: altera_avalon_st_idle_remover" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_idle_remover.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_idle_remover.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815657 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815657 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jtag_mm/synthesis/submodules/altera_avalon_st_idle_inserter.v 1 1 " "Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_idle_inserter.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_idle_inserter " "Found entity 1: altera_avalon_st_idle_inserter" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_idle_inserter.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_idle_inserter.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814815659 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814815659 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1433814815748 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM JTAG_MM:U_jtag_mm " "Elaborating entity \"JTAG_MM\" for hierarchy \"JTAG_MM:U_jtag_mm\"" {  } { { "top.v" "U_jtag_mm" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/top.v" 10 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815751 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_master_0 JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0 " "Elaborating entity \"JTAG_MM_master_0\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\"" {  } { { "JTAG_MM/synthesis/JTAG_MM.v" "master_0" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v" 46 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815755 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_jtag_interface JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master " "Elaborating entity \"altera_avalon_st_jtag_interface\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "jtag_phy_embedded_in_jtag_master" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 113 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815759 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_jtag_dc_streaming JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming " "Elaborating entity \"altera_jtag_dc_streaming\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\"" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v" "normal.jtag_dc_streaming" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v" 75 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815761 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "synchronizer" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 188 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815773 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer " "Elaborated megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 188 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814815774 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer " "Instantiated megafunction \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_std_synchronizer:synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 3 " "Parameter \"depth\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815774 ""}  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 188 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1433814815774 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_jtag_streaming JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming " "Elaborating entity \"altera_jtag_streaming\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "jtag_streaming" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815775 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "clock_sense_reset_n_synchronizer" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 241 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815789 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer " "Elaborated megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 241 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814815790 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer " "Instantiated megafunction \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:clock_sense_reset_n_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 8 " "Parameter \"depth\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815790 ""}  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 241 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1433814815790 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_jtag_sld_node JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node " "Elaborating entity \"altera_jtag_sld_node\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "node" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 557 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815792 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" "sld_virtual_jtag_component" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815805 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component " "Elaborated megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" 86 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component " "Instantiated megafunction \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 110 " "Parameter \"sld_mfg_id\" = \"110\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 132 " "Parameter \"sld_type_id\" = \"132\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 1 " "Parameter \"sld_version\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 3 " "Parameter \"sld_ir_width\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action  " "Parameter \"sld_sim_action\" = \"\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815806 ""}  } { { "JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" 86 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1433814815806 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" {  } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815808 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component " "Elaborated megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_jtag_sld_node:node\|sld_virtual_jtag_basic:sld_virtual_jtag_component\"" {  } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v" 86 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815810 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_idle_remover JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_avalon_st_idle_remover:idle_remover " "Elaborating entity \"altera_avalon_st_idle_remover\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_avalon_st_idle_remover:idle_remover\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "idle_remover" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 574 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815812 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_idle_inserter JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_avalon_st_idle_inserter:idle_inserter " "Elaborating entity \"altera_avalon_st_idle_inserter\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_avalon_st_idle_inserter:idle_inserter\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" "idle_inserter" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v" 591 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815814 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_clock_crosser JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_avalon_st_clock_crosser:sink_crosser " "Elaborating entity \"altera_avalon_st_clock_crosser\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_avalon_st_clock_crosser:sink_crosser\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "sink_crosser" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 230 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815817 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_pipeline_base JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_avalon_st_clock_crosser:sink_crosser\|altera_avalon_st_pipeline_base:output_stage " "Elaborating entity \"altera_avalon_st_pipeline_base\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_avalon_st_clock_crosser:sink_crosser\|altera_avalon_st_pipeline_base:output_stage\"" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v" "output_stage" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v" 129 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_jtag_src_crosser JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_src_crosser:source_crosser " "Elaborating entity \"altera_jtag_src_crosser\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_src_crosser:source_crosser\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "source_crosser" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 243 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815826 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_jtag_control_signal_crosser JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_src_crosser:source_crosser\|altera_jtag_control_signal_crosser:crosser " "Elaborating entity \"altera_jtag_control_signal_crosser\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_src_crosser:source_crosser\|altera_jtag_control_signal_crosser:crosser\"" {  } { { "JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" "crosser" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v" 97 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815828 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_master_0_timing_adt JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_timing_adt:timing_adt " "Elaborating entity \"JTAG_MM_master_0_timing_adt\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_timing_adt:timing_adt\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "timing_adt" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 123 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815835 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "fifo" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 164 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815838 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_bytes_to_packets JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_bytes_to_packets:b2p " "Elaborating entity \"altera_avalon_st_bytes_to_packets\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_bytes_to_packets:b2p\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "b2p" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815842 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_st_packets_to_bytes JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_packets_to_bytes:p2b " "Elaborating entity \"altera_avalon_st_packets_to_bytes\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_packets_to_bytes:p2b\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "p2b" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 198 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815845 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_packets_to_master JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_packets_to_master:transacto " "Elaborating entity \"altera_avalon_packets_to_master\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_packets_to_master:transacto\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "transacto" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 225 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815848 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "packets_to_master JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_packets_to_master:transacto\|packets_to_master:p2m " "Elaborating entity \"packets_to_master\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_packets_to_master:transacto\|packets_to_master:p2m\"" {  } { { "JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" "p2m" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v" 124 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815850 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_master_0_b2p_adapter JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_b2p_adapter:b2p_adapter " "Elaborating entity \"JTAG_MM_master_0_b2p_adapter\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_b2p_adapter:b2p_adapter\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "b2p_adapter" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 241 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815856 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "out_channel JTAG_MM_master_0_b2p_adapter.v(28) " "Verilog HDL or VHDL warning at JTAG_MM_master_0_b2p_adapter.v(28): object \"out_channel\" assigned a value but never read" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" 28 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1433814815857 "|top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_b2p_adapter:b2p_adapter"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 JTAG_MM_master_0_b2p_adapter.v(40) " "Verilog HDL assignment warning at JTAG_MM_master_0_b2p_adapter.v(40): truncated value with size 8 to match size of target (1)" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1433814815857 "|top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_b2p_adapter:b2p_adapter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_master_0_p2b_adapter JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_p2b_adapter:p2b_adapter " "Elaborating entity \"JTAG_MM_master_0_p2b_adapter\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|JTAG_MM_master_0_p2b_adapter:p2b_adapter\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "p2b_adapter" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 257 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815859 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" "rst_controller" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v" 320 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815862 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" {  } { { "JTAG_MM/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_controller.v" 208 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815864 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" {  } { { "JTAG_MM/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_controller.v" 220 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815867 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_POUT JTAG_MM:U_jtag_mm\|JTAG_MM_POUT:pout " "Elaborating entity \"JTAG_MM_POUT\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_POUT:pout\"" {  } { { "JTAG_MM/synthesis/JTAG_MM.v" "pout" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v" 57 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815870 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_PIN JTAG_MM:U_jtag_mm\|JTAG_MM_PIN:pin " "Elaborating entity \"JTAG_MM_PIN\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_PIN:pin\"" {  } { { "JTAG_MM/synthesis/JTAG_MM.v" "pin" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v" 65 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815873 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0 JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"JTAG_MM_mm_interconnect_0\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\"" {  } { { "JTAG_MM/synthesis/JTAG_MM.v" "mm_interconnect_0" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815876 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:master_0_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:master_0_master_translator\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "master_0_master_translator" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815890 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:pout_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:pout_s1_translator\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "pout_s1_translator" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 303 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815893 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "master_0_master_translator_avalon_universal_master_0_agent" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 451 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815899 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "pout_s1_translator_avalon_universal_slave_0_agent" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 534 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815903 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv" 581 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815907 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 575 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815912 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_addr_router JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_addr_router:addr_router " "Elaborating entity \"JTAG_MM_mm_interconnect_0_addr_router\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_addr_router:addr_router\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "addr_router" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 715 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815925 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_addr_router_default_decode JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_addr_router:addr_router\|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode " "Elaborating entity \"JTAG_MM_mm_interconnect_0_addr_router_default_decode\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_addr_router:addr_router\|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" "the_default_decode" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv" 187 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815927 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_id_router JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_id_router:id_router " "Elaborating entity \"JTAG_MM_mm_interconnect_0_id_router\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_id_router:id_router\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "id_router" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 731 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815930 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_id_router_default_decode JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_id_router:id_router\|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode " "Elaborating entity \"JTAG_MM_mm_interconnect_0_id_router_default_decode\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_id_router:id_router\|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" "the_default_decode" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv" 175 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815931 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:limiter\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "limiter" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 795 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815936 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_cmd_xbar_demux JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"JTAG_MM_mm_interconnect_0_cmd_xbar_demux\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "cmd_xbar_demux" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 818 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815940 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_cmd_xbar_mux JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"JTAG_MM_mm_interconnect_0_cmd_xbar_mux\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "cmd_xbar_mux" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 835 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815943 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_rsp_xbar_demux JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"JTAG_MM_mm_interconnect_0_rsp_xbar_demux\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "rsp_xbar_demux" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 869 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815948 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "JTAG_MM_mm_interconnect_0_rsp_xbar_mux JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"JTAG_MM_mm_interconnect_0_rsp_xbar_mux\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" "rsp_xbar_mux" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v" 909 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815953 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" {  } { { "JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv" "arb" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv" 296 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815957 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"JTAG_MM:U_jtag_mm\|JTAG_MM_mm_interconnect_0:mm_interconnect_0\|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814815959 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 6 " "Parameter WIDTHAD_A set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 64 " "Parameter NUMWORDS_A set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 6 " "Parameter WIDTHAD_B set to 6" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 64 " "Parameter NUMWORDS_B set to 64" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433814818264 ""}  } {  } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Quartus II" 0 -1 1433814818264 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1433814818264 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|altsyncram:mem_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814818320 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_sc_fifo:fifo\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 6 " "Parameter \"WIDTHAD_A\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 64 " "Parameter \"NUMWORDS_A\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 6 " "Parameter \"WIDTHAD_B\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 64 " "Parameter \"NUMWORDS_B\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433814818321 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1433814818321 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nog1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nog1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nog1 " "Found entity 1: altsyncram_nog1" {  } { { "db/altsyncram_nog1.tdf" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/db/altsyncram_nog1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433814818394 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433814818394 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1433814818680 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv" 279 -1 0 } } { "JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v" 165 -1 0 } } { "JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v" 123 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1433814818768 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1433814818768 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814819375 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "37 " "37 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1433814820006 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.map.smsg " "Generated suppressed messages file d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1433814820110 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1433814820485 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433814820485 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1050 " "Implemented 1050 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "14 " "Implemented 14 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1433814820672 ""} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Implemented 11 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1433814820672 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1016 " "Implemented 1016 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1433814820672 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1433814820672 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1433814820672 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "553 " "Peak virtual memory: 553 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1433814820721 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 09 09:53:40 2015 " "Processing ended: Tue Jun 09 09:53:40 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1433814820721 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1433814820721 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1433814820721 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1433814820721 ""}
