{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1433681346433 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Full Version " "Version 13.1.0 Build 162 10/23/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1433681346433 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 07 20:49:06 2015 " "Processing started: Sun Jun 07 20:49:06 2015" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1433681346433 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1433681346433 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top_sin_wave -c top_sin_wave " "Command: quartus_map --read_settings_files=on --write_settings_files=off top_sin_wave -c top_sin_wave" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1433681346433 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1433681346739 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/current/matlab_fpga_lab/lab2_mat_signal/hdl/src/powerup_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/powerup_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 powerup_reset " "Found entity 1: powerup_reset" {  } { { "../src/powerup_reset.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/powerup_reset.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346838 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681346838 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/current/matlab_fpga_lab/lab2_mat_signal/hdl/src/top_sin_wave.v 2 2 " "Found 2 design units, including 2 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/top_sin_wave.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_sin_wave " "Found entity 1: top_sin_wave" {  } { { "../src/top_sin_wave.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346841 ""} { "Info" "ISGN_ENTITY_NAME" "2 generate_freq_word " "Found entity 2: generate_freq_word" {  } { { "../src/top_sin_wave.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 108 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346841 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681346841 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/current/matlab_fpga_lab/lab2_mat_signal/hdl/src/button.v 1 1 " "Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/button.v" { { "Info" "ISGN_ENTITY_NAME" "1 button_in_out " "Found entity 1: button_in_out" {  } { { "../src/button.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/button.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346852 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681346852 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core.v 1 1 " "Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core.v" { { "Info" "ISGN_ENTITY_NAME" "1 dds_core_sin " "Found entity 1: dds_core_sin" {  } { { "../src/dds_core.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/dds_core.v" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346854 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681346854 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core_rom.v 1 1 " "Found 1 design units, including 1 entities, in source file /current/matlab_fpga_lab/lab2_mat_signal/hdl/src/dds_core_rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 DDS_CORE_ROM " "Found entity 1: DDS_CORE_ROM" {  } { { "../src/DDS_CORE_ROM.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/DDS_CORE_ROM.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681346865 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681346865 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pu_rst_W top_sin_wave.v(65) " "Verilog HDL Implicit Net warning at top_sin_wave.v(65): created implicit net for \"pu_rst_W\"" {  } { { "../src/top_sin_wave.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 65 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433681346866 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "top_sin_wave " "Elaborating entity \"top_sin_wave\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1433681346913 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "powerup_reset powerup_reset:U_PURST " "Elaborating entity \"powerup_reset\" for hierarchy \"powerup_reset:U_PURST\"" {  } { { "../src/top_sin_wave.v" "U_PURST" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 65 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681346946 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button_in_out button_in_out:U_BUTUP " "Elaborating entity \"button_in_out\" for hierarchy \"button_in_out:U_BUTUP\"" {  } { { "../src/top_sin_wave.v" "U_BUTUP" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681346997 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "generate_freq_word generate_freq_word:U_GFQWD " "Elaborating entity \"generate_freq_word\" for hierarchy \"generate_freq_word:U_GFQWD\"" {  } { { "../src/top_sin_wave.v" "U_GFQWD" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 88 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681347011 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds_core_sin dds_core_sin:U_DDS " "Elaborating entity \"dds_core_sin\" for hierarchy \"dds_core_sin:U_DDS\"" {  } { { "../src/top_sin_wave.v" "U_DDS" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 96 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681347024 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DDS_CORE_ROM dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom " "Elaborating entity \"DDS_CORE_ROM\" for hierarchy \"dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\"" {  } { { "../src/dds_core.v" "u_sinrom" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/dds_core.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681347040 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nq14.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nq14.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nq14 " "Found entity 1: altsyncram_nq14" {  } { { "db/altsyncram_nq14.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/altsyncram_nq14.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349010 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349010 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_krc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_krc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_krc " "Found entity 1: mux_krc" {  } { { "db/mux_krc.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/mux_krc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349278 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349278 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_4uf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_4uf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_4uf " "Found entity 1: decode_4uf" {  } { { "db/decode_4uf.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/decode_4uf.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349387 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349387 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_9fi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_9fi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_9fi " "Found entity 1: cntr_9fi" {  } { { "db/cntr_9fi.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_9fi.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349547 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349547 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_jfc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_jfc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_jfc " "Found entity 1: cmpr_jfc" {  } { { "db/cmpr_jfc.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_jfc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349622 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349622 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_d8j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_d8j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_d8j " "Found entity 1: cntr_d8j" {  } { { "db/cntr_d8j.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_d8j.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349717 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349717 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7fi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_7fi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7fi " "Found entity 1: cntr_7fi" {  } { { "db/cntr_7fi.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_7fi.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349855 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349855 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ifc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ifc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ifc " "Found entity 1: cmpr_ifc" {  } { { "db/cmpr_ifc.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_ifc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681349925 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681349925 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_p1j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_p1j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_p1j " "Found entity 1: cntr_p1j" {  } { { "db/cntr_p1j.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cntr_p1j.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681350021 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681350021 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_efc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_efc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_efc " "Found entity 1: cmpr_efc" {  } { { "db/cmpr_efc.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/cmpr_efc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681350090 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681350090 ""}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 12033 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433681350220 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|Ram0_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|Ram0_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Parameter OPERATION_MODE set to ROM" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 12 " "Parameter WIDTH_A set to 12" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Parameter WIDTHAD_A set to 10" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Parameter NUMWORDS_A set to 1024" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Parameter OUTDATA_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif " "Parameter INIT_FILE set to db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif" {  } {  } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Quartus II" 0 -1 1433681351185 ""}  } {  } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Quartus II" 0 -1 1433681351185 ""}  } {  } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1433681351185 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|altsyncram:Ram0_rtl_0 " "Elaborated megafunction instantiation \"dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|altsyncram:Ram0_rtl_0\"" {  } {  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|altsyncram:Ram0_rtl_0 " "Instantiated megafunction \"dds_core_sin:U_DDS\|DDS_CORE_ROM:u_sinrom\|altsyncram:Ram0_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE ROM " "Parameter \"OPERATION_MODE\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 12 " "Parameter \"WIDTH_A\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 10 " "Parameter \"WIDTHAD_A\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 1024 " "Parameter \"NUMWORDS_A\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif " "Parameter \"INIT_FILE\" = \"db/top_sin_wave.rom0_DDS_CORE_ROM_45dc2ebd.hdl.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1433681351235 ""}  } {  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1433681351235 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_k581.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_k581.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_k581 " "Found entity 1: altsyncram_k581" {  } { { "db/altsyncram_k581.tdf" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/prj_q131/db/altsyncram_k581.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1433681351301 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1433681351301 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "../src/top_sin_wave.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 160 -1 0 } } { "../src/top_sin_wave.v" "" { Text "D:/current/MATLAB_FPGA_LAB/LAB2_MAT_Signal/hdl/src/top_sin_wave.v" 122 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1433681352554 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1433681352554 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_buffer_manager.vhd" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1433681352827 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1433681352827 ""}
{ "Warning" "WFTM_IGNORED_NOT_GATE_PUSH_ASSIGNMENT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff " "The assignment to disallow NOT gate push-back on register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|trigger_out_mode_ff\" is ignored" {  } { { "sld_signaltap_impl.vhd" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 975 -1 0 } }  } 0 18057 "The assignment to disallow NOT gate push-back on register \"%1!s!\" is ignored" 0 0 "Quartus II" 0 -1 1433681353084 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 257 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 389 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1433681353707 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1433681353707 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" {  } { { "sld_hub.vhd" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/sld_hub.vhd" 326 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1433681353759 "|top_sin_wave|sld_hub:auto_hub|receive[0][0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1433681353759 ""}
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 89 " "Succesfully connected in-system debug instance \"auto_signaltap_0\" to all 89 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" {  } {  } 0 35024 "Succesfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Quartus II" 0 -1 1433681354435 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1433681354473 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1433681354473 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1683 " "Implemented 1683 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Implemented 7 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1433681354924 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1433681354924 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1605 " "Implemented 1605 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1433681354924 ""} { "Info" "ICUT_CUT_TM_RAMS" "56 " "Implemented 56 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1433681354924 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1433681354924 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "551 " "Peak virtual memory: 551 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1433681354956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 07 20:49:14 2015 " "Processing ended: Sun Jun 07 20:49:14 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1433681354956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1433681354956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1433681354956 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1433681354956 ""}
