<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element PIN
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element POUT
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element clk_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element master_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element PIN.s1
   {
      datum baseAddress
      {
         value = "0";
         type = "String";
      }
   }
   element POUT.s1
   {
      datum baseAddress
      {
         value = "16";
         type = "String";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="device" value="EP3C16F484C6" />
 <parameter name="deviceFamily" value="Cyclone III" />
 <parameter name="deviceSpeedGrade" value="6" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="1" />
 <parameter name="projectName" value="" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="0" />
 <parameter name="timeStamp" value="0" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
 <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
 <interface
   name="pout"
   internal="POUT.external_connection"
   type="conduit"
   dir="end" />
 <interface
   name="pin"
   internal="PIN.external_connection"
   type="conduit"
   dir="end" />
 <module kind="clock_source" version="13.1" enabled="1" name="clk_0">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_jtag_avalon_master"
   version="13.1"
   enabled="1"
   name="master_0">
  <parameter name="USE_PLI" value="0" />
  <parameter name="PLI_PORT" value="50000" />
  <parameter name="COMPONENT_CLOCK" value="0" />
  <parameter name="FAST_VER" value="0" />
  <parameter name="FIFO_DEPTHS" value="2" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone III" />
  <parameter name="AUTO_DEVICE" value="EP3C16F484C6" />
 </module>
 <module kind="altera_avalon_pio" version="13.1" enabled="1" name="POUT">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="8" />
  <parameter name="clockRate" value="50000000" />
 </module>
 <module kind="altera_avalon_pio" version="13.1" enabled="1" name="PIN">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="8" />
  <parameter name="clockRate" value="50000000" />
 </module>
 <connection
   kind="reset"
   version="13.1"
   start="clk_0.clk_reset"
   end="master_0.clk_reset" />
 <connection kind="reset" version="13.1" start="clk_0.clk_reset" end="POUT.reset" />
 <connection kind="reset" version="13.1" start="clk_0.clk_reset" end="PIN.reset" />
 <connection kind="clock" version="13.1" start="clk_0.clk" end="master_0.clk" />
 <connection kind="clock" version="13.1" start="clk_0.clk" end="POUT.clk" />
 <connection kind="clock" version="13.1" start="clk_0.clk" end="PIN.clk" />
 <connection kind="avalon" version="13.1" start="master_0.master" end="POUT.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0010" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <connection kind="avalon" version="13.1" start="master_0.master" end="PIN.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
  <parameter name="defaultConnection" value="false" />
 </connection>
 <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
 <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
 <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
</system>
