{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1433814822674 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "top EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1433814822706 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1433814822757 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1433814822758 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1433814822758 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1433814822882 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1433814823152 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1433814823152 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1433814823152 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1433814823152 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2166 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1433814823165 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2168 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1433814823165 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2170 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1433814823165 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2172 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1433814823165 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2174 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1433814823165 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1433814823165 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1433814823169 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1433814823173 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_avalon_st_clock_crosser " "Entity altera_avalon_st_clock_crosser" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\] " "set_false_path -from \[get_registers *altera_avalon_st_clock_crosser:*\|in_data_buffer*\] -to \[get_registers *altera_avalon_st_clock_crosser:*\|out_data_buffer*\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1433814824447 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1433814824447 ""}
{ "Info" "ISTA_SDC_FOUND" "JTAG_MM/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'JTAG_MM/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1433814824456 ""}
{ "Info" "ISTA_SDC_FOUND" "JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.sdc " "Reading SDC File: 'JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1433814824461 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1433814824465 "|top|CLOCK_50"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1433814824475 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1433814824475 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1433814824475 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1433814824475 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824476 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824476 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1433814824476 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1433814824476 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1433814824555 ""}  } { { "top.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/top.v" 2 0 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 2148 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1433814824555 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1433814824556 ""}  } { { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 1836 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1433814824556 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out  " "Automatically promoted node JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1433814824556 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:reset_to_sample_synchronizer\|din_s1 " "Destination node JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:reset_to_sample_synchronizer\|din_s1" {  } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "JTAG_MM:U_jtag_mm\|JTAG_MM_master_0:master_0\|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master\|altera_jtag_dc_streaming:normal.jtag_dc_streaming\|altera_jtag_streaming:jtag_streaming\|altera_std_synchronizer:reset_to_sample_synchronizer\|din_s1" } } } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|din_s1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 876 9662 10382 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1433814824556 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1433814824556 ""}  } { { "JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 318 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1433814824556 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "JTAG_MM:U_jtag_mm\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out  " "Automatically promoted node JTAG_MM:U_jtag_mm\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1433814824557 ""}  } { { "JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 0 { 0 ""} 0 820 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1433814824557 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1433814824853 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1433814824856 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1433814824856 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1433814824859 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1433814824862 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1433814824865 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1433814824866 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1433814824868 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1433814824907 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" {  } {  } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1433814824910 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1433814824910 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTON \[0\] " "Node \"BUTTON \[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON \[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTON \[1\] " "Node \"BUTTON \[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON \[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "BUTTON \[2\] " "Node \"BUTTON \[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON \[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50_2 " "Node \"CLOCK_50_2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[0\] " "Node \"HEX0_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[1\] " "Node \"HEX0_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[2\] " "Node \"HEX0_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[3\] " "Node \"HEX0_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[4\] " "Node \"HEX0_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[5\] " "Node \"HEX0_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_D\[6\] " "Node \"HEX0_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[0\] " "Node \"HEX1_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[1\] " "Node \"HEX1_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[2\] " "Node \"HEX1_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[3\] " "Node \"HEX1_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[4\] " "Node \"HEX1_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[5\] " "Node \"HEX1_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[6\] " "Node \"HEX1_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[0\] " "Node \"HEX2_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[1\] " "Node \"HEX2_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[2\] " "Node \"HEX2_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[3\] " "Node \"HEX2_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[4\] " "Node \"HEX2_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[5\] " "Node \"HEX2_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[6\] " "Node \"HEX2_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[0\] " "Node \"HEX3_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[1\] " "Node \"HEX3_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[2\] " "Node \"HEX3_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[3\] " "Node \"HEX3_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[4\] " "Node \"HEX3_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[5\] " "Node \"HEX3_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[6\] " "Node \"HEX3_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1433814824985 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1433814824985 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1433814824991 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1433814825702 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1433814825998 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1433814826014 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1433814826534 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1433814826534 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1433814826971 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Router estimated average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X21_Y20 X30_Y29 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29" {  } { { "loc" "" { Generic "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} 21 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1433814827857 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1433814827857 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1433814828013 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1433814828014 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1433814828014 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1433814828014 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1433814828050 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1433814828092 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1433814828476 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1433814828512 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1433814828918 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1433814829466 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1433814830371 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.fit.smsg " "Generated suppressed messages file d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1433814830545 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 96 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 96 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1131 " "Peak virtual memory: 1131 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1433814831067 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 09 09:53:51 2015 " "Processing ended: Tue Jun 09 09:53:51 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1433814831067 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1433814831067 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1433814831067 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1433814831067 ""}
