Fitter report for top
Tue Jun 09 09:53:50 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. I/O Assignment Warnings
  6. Fitter Netlist Optimizations
  7. Ignored Assignments
  8. Incremental Compilation Preservation Summary
  9. Incremental Compilation Partition Settings
 10. Incremental Compilation Placement Preservation
 11. Pin-Out File
 12. Fitter Resource Usage Summary
 13. Fitter Partition Statistics
 14. Input Pins
 15. Output Pins
 16. Dual Purpose and Dedicated Pins
 17. I/O Bank Usage
 18. All Package Pins
 19. Fitter Resource Utilization by Entity
 20. Delay Chain Summary
 21. Pad To Core Delay Chain Fanout
 22. Control Signals
 23. Global & Other Fast Signals
 24. Non-Global High Fan-Out Signals
 25. Fitter RAM Summary
 26. Routing Usage Summary
 27. LAB Logic Elements
 28. LAB-wide Signals
 29. LAB Signals Sourced
 30. LAB Signals Sourced Out
 31. LAB Distinct Inputs
 32. I/O Rules Summary
 33. I/O Rules Details
 34. I/O Rules Matrix
 35. Fitter Device Options
 36. Operating Settings and Conditions
 37. Fitter Messages
 38. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Tue Jun 09 09:53:50 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; top                                         ;
; Top-level Entity Name              ; top                                         ;
; Family                             ; Cyclone III                                 ;
; Device                             ; EP3C16F484C6                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 933 / 15,408 ( 6 % )                        ;
;     Total combinational functions  ; 787 / 15,408 ( 5 % )                        ;
;     Dedicated logic registers      ; 514 / 15,408 ( 3 % )                        ;
; Total registers                    ; 514                                         ;
; Total pins                         ; 21 / 347 ( 6 % )                            ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 512 / 516,096 ( < 1 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
; Total PLLs                         ; 0 / 4 ( 0 % )                               ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                            ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                     ; Setting                               ; Default Value                         ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                     ; EP3C16F484C6                          ;                                       ;
; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
; Use smart compilation                                                      ; Off                                   ; Off                                   ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
; Enable compact report table                                                ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                           ; Off                                   ; Off                                   ;
; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
; PCI I/O                                                                    ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                          ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                          ; On                                    ; On                                    ;
; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ; < 0.1%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------+
; I/O Assignment Warnings                         ;
+----------+--------------------------------------+
; Pin Name ; Reason                               ;
+----------+--------------------------------------+
; LEDG[0]  ; Missing drive strength and slew rate ;
; LEDG[1]  ; Missing drive strength and slew rate ;
; LEDG[2]  ; Missing drive strength and slew rate ;
; LEDG[3]  ; Missing drive strength and slew rate ;
; LEDG[4]  ; Missing drive strength and slew rate ;
; LEDG[5]  ; Missing drive strength and slew rate ;
; LEDG[6]  ; Missing drive strength and slew rate ;
; LEDG[7]  ; Missing drive strength and slew rate ;
; LEDG[8]  ; Missing drive strength and slew rate ;
; LEDG[9]  ; Missing drive strength and slew rate ;
+----------+--------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node                                                                                  ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node                                                                                                                        ; Destination Port ; Destination Port Name ;
+---------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[0] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a0 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[1] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a1 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[2] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a2 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[3] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a3 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[4] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a4 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[5] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a5 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[6] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a6 ; PORTBDATAOUT     ;                       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[7] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ram_block1a7 ; PORTBDATAOUT     ;                       ;
+---------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+


+-------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                       ;
+----------+----------------+--------------+---------------+---------------+----------------+
; Name     ; Ignored Entity ; Ignored From ; Ignored To    ; Ignored Value ; Ignored Source ;
+----------+----------------+--------------+---------------+---------------+----------------+
; Location ;                ;              ; BUTTON [0]    ; PIN_ H2       ; QSF Assignment ;
; Location ;                ;              ; BUTTON [1]    ; PIN_ G3       ; QSF Assignment ;
; Location ;                ;              ; BUTTON [2]    ; PIN_ F1       ; QSF Assignment ;
; Location ;                ;              ; CLOCK_50_2    ; PIN_B12       ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[0]  ; PIN_C4        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[10] ; PIN_B4        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[11] ; PIN_A7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[12] ; PIN_C8        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[1]  ; PIN_A3        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[2]  ; PIN_B3        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[3]  ; PIN_C3        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[4]  ; PIN_A5        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[5]  ; PIN_C6        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[6]  ; PIN_B6        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[7]  ; PIN_A6        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[8]  ; PIN_C7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_ADDR[9]  ; PIN_B7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_BA_0     ; PIN_B5        ; QSF Assignment ;
; Location ;                ;              ; DRAM_BA_1     ; PIN_A4        ; QSF Assignment ;
; Location ;                ;              ; DRAM_CAS_N    ; PIN_G8        ; QSF Assignment ;
; Location ;                ;              ; DRAM_CKE      ; PIN_E6        ; QSF Assignment ;
; Location ;                ;              ; DRAM_CLK      ; PIN_E5        ; QSF Assignment ;
; Location ;                ;              ; DRAM_CS_N     ; PIN_G7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[0]    ; PIN_D10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[10]   ; PIN_A9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[11]   ; PIN_C10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[12]   ; PIN_B10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[13]   ; PIN_A10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[14]   ; PIN_E10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[15]   ; PIN_F10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[1]    ; PIN_G10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[2]    ; PIN_H10       ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[3]    ; PIN_E9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[4]    ; PIN_F9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[5]    ; PIN_G9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[6]    ; PIN_H9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[7]    ; PIN_F8        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[8]    ; PIN_A8        ; QSF Assignment ;
; Location ;                ;              ; DRAM_DQ[9]    ; PIN_B9        ; QSF Assignment ;
; Location ;                ;              ; DRAM_LDQM     ; PIN_E7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_RAS_N    ; PIN_F7        ; QSF Assignment ;
; Location ;                ;              ; DRAM_UDQM     ; PIN_B8        ; QSF Assignment ;
; Location ;                ;              ; DRAM_WE_N     ; PIN_D6        ; QSF Assignment ;
; Location ;                ;              ; HEX0_DP       ; PIN_D13       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[0]     ; PIN_E11       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[1]     ; PIN_F11       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[2]     ; PIN_H12       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[3]     ; PIN_H13       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[4]     ; PIN_G12       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[5]     ; PIN_F12       ; QSF Assignment ;
; Location ;                ;              ; HEX0_D[6]     ; PIN_F13       ; QSF Assignment ;
; Location ;                ;              ; HEX1_DP       ; PIN_B15       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[0]     ; PIN_A13       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[1]     ; PIN_B13       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[2]     ; PIN_C13       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[3]     ; PIN_A14       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[4]     ; PIN_B14       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[5]     ; PIN_E14       ; QSF Assignment ;
; Location ;                ;              ; HEX1_D[6]     ; PIN_A15       ; QSF Assignment ;
; Location ;                ;              ; HEX2_DP       ; PIN_A18       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[0]     ; PIN_D15       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[1]     ; PIN_A16       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[2]     ; PIN_B16       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[3]     ; PIN_E15       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[4]     ; PIN_A17       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[5]     ; PIN_B17       ; QSF Assignment ;
; Location ;                ;              ; HEX2_D[6]     ; PIN_F14       ; QSF Assignment ;
; Location ;                ;              ; HEX3_DP       ; PIN_G16       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[0]     ; PIN_B18       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[1]     ; PIN_F15       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[2]     ; PIN_A19       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[3]     ; PIN_B19       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[4]     ; PIN_C19       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[5]     ; PIN_D19       ; QSF Assignment ;
; Location ;                ;              ; HEX3_D[6]     ; PIN_G15       ; QSF Assignment ;
; Location ;                ;              ; VGA_B[0]      ; PIN_K22       ; QSF Assignment ;
; Location ;                ;              ; VGA_B[1]      ; PIN_K21       ; QSF Assignment ;
; Location ;                ;              ; VGA_B[2]      ; PIN_J22       ; QSF Assignment ;
; Location ;                ;              ; VGA_B[3]      ; PIN_K18       ; QSF Assignment ;
; Location ;                ;              ; VGA_G[0]      ; PIN_H22       ; QSF Assignment ;
; Location ;                ;              ; VGA_G[1]      ; PIN_J17       ; QSF Assignment ;
; Location ;                ;              ; VGA_G[2]      ; PIN_K17       ; QSF Assignment ;
; Location ;                ;              ; VGA_G[3]      ; PIN_J21       ; QSF Assignment ;
; Location ;                ;              ; VGA_HS        ; PIN_L21       ; QSF Assignment ;
; Location ;                ;              ; VGA_R[0]      ; PIN_H19       ; QSF Assignment ;
; Location ;                ;              ; VGA_R[1]      ; PIN_H17       ; QSF Assignment ;
; Location ;                ;              ; VGA_R[2]      ; PIN_H20       ; QSF Assignment ;
; Location ;                ;              ; VGA_R[3]      ; PIN_H21       ; QSF Assignment ;
; Location ;                ;              ; VGA_VS        ; PIN_L22       ; QSF Assignment ;
+----------+----------------+--------------+---------------+---------------+----------------+


+---------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                      ;
+---------------------+---------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 1377 ) ; 0.00 % ( 0 / 1377 )        ; 0.00 % ( 0 / 1377 )      ;
;     -- Achieved     ; 0.00 % ( 0 / 1377 ) ; 0.00 % ( 0 / 1377 )        ; 0.00 % ( 0 / 1377 )      ;
;                     ;                     ;                            ;                          ;
; Routing (by net)    ;                     ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+---------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; sld_hub:auto_hub               ; Auto-generated ; Post-Synthesis    ; N/A                     ; Post-Synthesis         ; N/A                          ; sld_hub:auto_hub               ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 1177 )   ; N/A                     ; Source File       ; N/A                 ;       ;
; sld_hub:auto_hub               ; 0.00 % ( 0 / 190 )    ; N/A                     ; Post-Synthesis    ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.pin.


+-----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                         ;
+---------------------------------------------+-------------------------+
; Resource                                    ; Usage                   ;
+---------------------------------------------+-------------------------+
; Total logic elements                        ; 933 / 15,408 ( 6 % )    ;
;     -- Combinational with no register       ; 419                     ;
;     -- Register only                        ; 146                     ;
;     -- Combinational with a register        ; 368                     ;
;                                             ;                         ;
; Logic element usage by number of LUT inputs ;                         ;
;     -- 4 input functions                    ; 375                     ;
;     -- 3 input functions                    ; 190                     ;
;     -- <=2 input functions                  ; 222                     ;
;     -- Register only                        ; 146                     ;
;                                             ;                         ;
; Logic elements by mode                      ;                         ;
;     -- normal mode                          ; 675                     ;
;     -- arithmetic mode                      ; 112                     ;
;                                             ;                         ;
; Total registers*                            ; 514 / 17,068 ( 3 % )    ;
;     -- Dedicated logic registers            ; 514 / 15,408 ( 3 % )    ;
;     -- I/O registers                        ; 0 / 1,660 ( 0 % )       ;
;                                             ;                         ;
; Total LABs:  partially or completely used   ; 74 / 963 ( 8 % )        ;
; Virtual pins                                ; 0                       ;
; I/O pins                                    ; 21 / 347 ( 6 % )        ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )          ;
;     -- Dedicated input pins                 ; 3 / 9 ( 33 % )          ;
;                                             ;                         ;
; Global signals                              ; 4                       ;
; M9Ks                                        ; 1 / 56 ( 2 % )          ;
; Total block memory bits                     ; 512 / 516,096 ( < 1 % ) ;
; Total block memory implementation bits      ; 9,216 / 516,096 ( 2 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )         ;
; PLLs                                        ; 0 / 4 ( 0 % )           ;
; Global clocks                               ; 4 / 20 ( 20 % )         ;
; JTAGs                                       ; 1 / 1 ( 100 % )         ;
; CRC blocks                                  ; 0 / 1 ( 0 % )           ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )           ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )           ;
; Average interconnect usage (total/H/V)      ; 1% / 1% / 1%            ;
; Peak interconnect usage (total/H/V)         ; 5% / 5% / 5%            ;
; Maximum fan-out                             ; 296                     ;
; Highest non-global fan-out                  ; 46                      ;
; Total fan-out                               ; 4406                    ;
; Average fan-out                             ; 3.00                    ;
+---------------------------------------------+-------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+
; Statistic                                   ; Top                 ; sld_hub:auto_hub      ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                   ; Low                            ;
;                                             ;                     ;                       ;                                ;
; Total logic elements                        ; 803 / 15408 ( 5 % ) ; 130 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
;     -- Combinational with no register       ; 367                 ; 52                    ; 0                              ;
;     -- Register only                        ; 128                 ; 18                    ; 0                              ;
;     -- Combinational with a register        ; 308                 ; 60                    ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                       ;                                ;
;     -- 4 input functions                    ; 327                 ; 48                    ; 0                              ;
;     -- 3 input functions                    ; 164                 ; 26                    ; 0                              ;
;     -- <=2 input functions                  ; 184                 ; 38                    ; 0                              ;
;     -- Register only                        ; 128                 ; 18                    ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Logic elements by mode                      ;                     ;                       ;                                ;
;     -- normal mode                          ; 571                 ; 104                   ; 0                              ;
;     -- arithmetic mode                      ; 104                 ; 8                     ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Total registers                             ; 436                 ; 78                    ; 0                              ;
;     -- Dedicated logic registers            ; 436 / 15408 ( 3 % ) ; 78 / 15408 ( < 1 % )  ; 0 / 15408 ( 0 % )              ;
;     -- I/O registers                        ; 0                   ; 0                     ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Total LABs:  partially or completely used   ; 62 / 963 ( 6 % )    ; 13 / 963 ( 1 % )      ; 0 / 963 ( 0 % )                ;
;                                             ;                     ;                       ;                                ;
; Virtual pins                                ; 0                   ; 0                     ; 0                              ;
; I/O pins                                    ; 21                  ; 0                     ; 0                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
; Total memory bits                           ; 512                 ; 0                     ; 0                              ;
; Total RAM block bits                        ; 9216                ; 0                     ; 0                              ;
; JTAG                                        ; 1 / 1 ( 100 % )     ; 0 / 1 ( 0 % )         ; 0 / 1 ( 0 % )                  ;
; M9K                                         ; 1 / 56 ( 1 % )      ; 0 / 56 ( 0 % )        ; 0 / 56 ( 0 % )                 ;
; Clock control block                         ; 4 / 24 ( 16 % )     ; 0 / 24 ( 0 % )        ; 0 / 24 ( 0 % )                 ;
;                                             ;                     ;                       ;                                ;
; Connections                                 ;                     ;                       ;                                ;
;     -- Input Connections                    ; 352                 ; 115                   ; 0                              ;
;     -- Registered Input Connections         ; 221                 ; 86                    ; 0                              ;
;     -- Output Connections                   ; 339                 ; 128                   ; 0                              ;
;     -- Registered Output Connections        ; 0                   ; 127                   ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Internal Connections                        ;                     ;                       ;                                ;
;     -- Total Connections                    ; 3910                ; 743                   ; 5                              ;
;     -- Registered Connections               ; 1386                ; 523                   ; 0                              ;
;                                             ;                     ;                       ;                                ;
; External Connections                        ;                     ;                       ;                                ;
;     -- Top                                  ; 448                 ; 243                   ; 0                              ;
;     -- sld_hub:auto_hub                     ; 243                 ; 0                     ; 0                              ;
;     -- hard_block:auto_generated_inst       ; 0                   ; 0                     ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Partition Interface                         ;                     ;                       ;                                ;
;     -- Input Ports                          ; 39                  ; 15                    ; 0                              ;
;     -- Output Ports                         ; 15                  ; 33                    ; 0                              ;
;     -- Bidir Ports                          ; 0                   ; 0                     ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Registered Ports                            ;                     ;                       ;                                ;
;     -- Registered Input Ports               ; 0                   ; 4                     ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 22                    ; 0                              ;
;                                             ;                     ;                       ;                                ;
; Port Connectivity                           ;                     ;                       ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 5                     ; 0                              ;
;     -- Output Ports driven by GND           ; 0                   ; 1                     ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                     ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                     ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 1                     ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                     ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 2                     ; 0                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 22                    ; 0                              ;
+---------------------------------------------+---------------------+-----------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                    ;
+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
; CLOCK_50 ; G21   ; 6        ; 41           ; 15           ; 0            ; 219                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[0]    ; J6    ; 1        ; 0            ; 24           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[1]    ; H5    ; 1        ; 0            ; 27           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[2]    ; H6    ; 1        ; 0            ; 25           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[3]    ; G4    ; 1        ; 0            ; 23           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[4]    ; G5    ; 1        ; 0            ; 27           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[5]    ; J7    ; 1        ; 0            ; 22           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[6]    ; H7    ; 1        ; 0            ; 25           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[7]    ; E3    ; 1        ; 0            ; 26           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[8]    ; E4    ; 1        ; 0            ; 26           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
; SW[9]    ; D2    ; 1        ; 0            ; 25           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; LEDG[0] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[1] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[2] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[3] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[4] ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[5] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[6] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[7] ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[8] ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; LEDG[9] ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                         ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
; L5       ; TDI                         ; -                        ; altera_reserved_tdi     ; JTAG Pin                  ;
; L2       ; TCK                         ; -                        ; altera_reserved_tck     ; JTAG Pin                  ;
; L1       ; TMS                         ; -                        ; altera_reserved_tms     ; JTAG Pin                  ;
; L4       ; TDO                         ; -                        ; altera_reserved_tdo     ; JTAG Pin                  ;
; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+----------+-----------------------------+--------------------------+-------------------------+---------------------------+


+------------------------------------------------------------+
; I/O Bank Usage                                             ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1        ; 24 / 33 ( 73 % ) ; 2.5V          ; --           ;
; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
; 6        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
+----------+------------------+---------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                                        ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
; L1       ; 35         ; 1        ; altera_reserved_tms                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L2       ; 34         ; 1        ; altera_reserved_tck                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L4       ; 36         ; 1        ; altera_reserved_tdo                                       ; output ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L5       ; 33         ; 1        ; altera_reserved_tdi                                       ; input  ; 2.5 V        ;         ; --         ; N               ; no       ; Off          ;
; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                       ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                                                                                                                        ; Library Name ;
+--------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |top                                                                                             ; 933 (1)     ; 514 (0)                   ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 21   ; 0            ; 419 (1)      ; 146 (0)           ; 368 (0)          ; |top                                                                                                                                                                                                                                                                                       ; work         ;
;    |JTAG_MM:U_jtag_mm|                                                                           ; 802 (0)     ; 436 (0)                   ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 366 (0)      ; 128 (0)           ; 308 (0)          ; |top|JTAG_MM:U_jtag_mm                                                                                                                                                                                                                                                                     ; JTAG_MM      ;
;       |JTAG_MM_PIN:pin|                                                                          ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin                                                                                                                                                                                                                                                     ; JTAG_MM      ;
;       |JTAG_MM_POUT:pout|                                                                        ; 18 (18)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 8 (8)             ; 8 (8)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout                                                                                                                                                                                                                                                   ; JTAG_MM      ;
;       |JTAG_MM_master_0:master_0|                                                                ; 722 (0)     ; 378 (0)                   ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 343 (0)      ; 116 (0)           ; 263 (0)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0                                                                                                                                                                                                                                           ; JTAG_MM      ;
;          |altera_avalon_packets_to_master:transacto|                                             ; 197 (0)     ; 69 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 125 (0)      ; 8 (0)             ; 64 (0)           ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto                                                                                                                                                                                                 ; JTAG_MM      ;
;             |packets_to_master:p2m|                                                              ; 197 (197)   ; 69 (69)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 125 (125)    ; 8 (8)             ; 64 (64)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m                                                                                                                                                                           ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:fifo|                                                            ; 32 (32)     ; 16 (16)                   ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 16 (16)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo                                                                                                                                                                                                                ; JTAG_MM      ;
;             |altsyncram:mem_rtl_0|                                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0                                                                                                                                                                                           ; work         ;
;                |altsyncram_nog1:auto_generated|                                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 512         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated                                                                                                                                                            ; work         ;
;          |altera_avalon_st_bytes_to_packets:b2p|                                                 ; 23 (23)     ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 6 (6)             ; 8 (8)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p                                                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|                      ; 441 (0)     ; 263 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 178 (0)      ; 100 (0)           ; 163 (0)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master                                                                                                                                                                          ; JTAG_MM      ;
;             |altera_jtag_dc_streaming:normal.jtag_dc_streaming|                                  ; 441 (0)     ; 263 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 178 (0)      ; 100 (0)           ; 163 (0)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming                                                                                                                        ; JTAG_MM      ;
;                |altera_avalon_st_clock_crosser:sink_crosser|                                     ; 49 (18)     ; 47 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 33 (16)           ; 14 (4)           ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser                                                                            ; JTAG_MM      ;
;                   |altera_avalon_st_pipeline_base:output_stage|                                  ; 20 (20)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 8 (8)             ; 10 (10)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage                                ; JTAG_MM      ;
;                   |altera_std_synchronizer:in_to_out_synchronizer|                               ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer                             ; work         ;
;                   |altera_std_synchronizer:out_to_in_synchronizer|                               ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer                             ; work         ;
;                |altera_jtag_src_crosser:source_crosser|                                          ; 27 (18)     ; 27 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 24 (15)           ; 3 (2)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser                                                                                 ; JTAG_MM      ;
;                   |altera_jtag_control_signal_crosser:crosser|                                   ; 10 (2)      ; 9 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (1)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser                                      ; JTAG_MM      ;
;                      |altera_std_synchronizer:synchronizer|                                      ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; work         ;
;                |altera_jtag_streaming:jtag_streaming|                                            ; 364 (334)   ; 186 (167)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 176 (168)    ; 41 (25)           ; 147 (137)        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming                                                                                   ; JTAG_MM      ;
;                   |altera_avalon_st_idle_inserter:idle_inserter|                                 ; 6 (6)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter                                      ; JTAG_MM      ;
;                   |altera_avalon_st_idle_remover:idle_remover|                                   ; 8 (8)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover                                        ; JTAG_MM      ;
;                   |altera_jtag_sld_node:node|                                                    ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 1 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node                                                         ; JTAG_MM      ;
;                      |sld_virtual_jtag_basic:sld_virtual_jtag_component|                         ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component       ; work         ;
;                   |altera_std_synchronizer:clock_sense_reset_n_synchronizer|                     ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer                          ; work         ;
;                   |altera_std_synchronizer:clock_sensor_synchronizer|                            ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer                                 ; work         ;
;                   |altera_std_synchronizer:clock_to_sample_div2_synchronizer|                    ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer                         ; work         ;
;                   |altera_std_synchronizer:reset_to_sample_synchronizer|                         ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer                              ; work         ;
;                |altera_std_synchronizer:synchronizer|                                            ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer                                                                                   ; work         ;
;          |altera_avalon_st_packets_to_bytes:p2b|                                                 ; 30 (30)     ; 15 (15)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 15 (15)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b                                                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_reset_controller:rst_controller|                                                ; 3 (0)       ; 3 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 1 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller                                                                                                                                                                                                    ; JTAG_MM      ;
;             |altera_reset_synchronizer:alt_rst_sync_uq1|                                         ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                         ; JTAG_MM      ;
;       |JTAG_MM_mm_interconnect_0:mm_interconnect_0|                                              ; 60 (0)      ; 39 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (0)       ; 2 (0)             ; 37 (0)           ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                                                                         ; JTAG_MM      ;
;          |JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|                               ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux                                                                                                                                                                 ; JTAG_MM      ;
;          |JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|                                   ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|       ; 8 (8)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 1 (1)             ; 5 (5)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo                                                                                                                                         ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|      ; 7 (7)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 5 (5)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo                                                                                                                                        ; JTAG_MM      ;
;          |altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent| ; 4 (4)       ; 1 (1)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 2 (2)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent                                                                                                                                   ; JTAG_MM      ;
;          |altera_merlin_slave_translator:pin_s1_translator|                                      ; 14 (14)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 11 (11)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator                                                                                                                                                                        ; JTAG_MM      ;
;          |altera_merlin_slave_translator:pout_s1_translator|                                     ; 16 (16)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 12 (12)          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator                                                                                                                                                                       ; JTAG_MM      ;
;          |altera_merlin_traffic_limiter:limiter|                                                 ; 9 (9)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 5 (5)            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter                                                                                                                                                                                   ; JTAG_MM      ;
;       |altera_reset_controller:rst_controller|                                                   ; 3 (0)       ; 3 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 1 (0)            ; |top|JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller                                                                                                                                                                                                                              ; JTAG_MM      ;
;          |altera_reset_synchronizer:alt_rst_sync_uq1|                                            ; 3 (3)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 1 (1)            ; |top|JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                   ; JTAG_MM      ;
;    |sld_hub:auto_hub|                                                                            ; 130 (1)     ; 78 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 52 (1)       ; 18 (0)            ; 60 (0)           ; |top|sld_hub:auto_hub                                                                                                                                                                                                                                                                      ; work         ;
;       |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|                                             ; 129 (89)    ; 78 (50)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 51 (39)      ; 18 (18)           ; 60 (35)          ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst                                                                                                                                                                                                                         ; work         ;
;          |sld_rom_sr:hub_info_reg|                                                               ; 20 (20)     ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (11)      ; 0 (0)             ; 9 (9)            ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg                                                                                                                                                                                                 ; work         ;
;          |sld_shadow_jsm:shadow_jsm|                                                             ; 20 (20)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 19 (19)          ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                               ; work         ;
+--------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                      ;
+----------+----------+---------------+---------------+-----------------------+-----+------+
; Name     ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
+----------+----------+---------------+---------------+-----------------------+-----+------+
; LEDG[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[7]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[8]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; LEDG[9]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
; SW[8]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[9]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; CLOCK_50 ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
; SW[2]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[1]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[5]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[7]    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; SW[6]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[4]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
; SW[3]    ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
; SW[0]    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+----------+----------+---------------+---------------+-----------------------+-----+------+


+----------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                                         ;
+----------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                                      ; Pad To Core Index ; Setting ;
+----------------------------------------------------------+-------------------+---------+
; SW[8]                                                    ;                   ;         ;
;      - LEDG[8]~output                                    ; 0                 ; 6       ;
; SW[9]                                                    ;                   ;         ;
;      - LEDG[9]~output                                    ; 0                 ; 6       ;
; CLOCK_50                                                 ;                   ;         ;
; SW[2]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[2] ; 0                 ; 6       ;
; SW[1]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[1] ; 0                 ; 6       ;
; SW[5]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[5] ; 0                 ; 6       ;
; SW[7]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[7] ; 1                 ; 6       ;
; SW[6]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[6] ; 0                 ; 6       ;
; SW[4]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[4] ; 0                 ; 6       ;
; SW[3]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[3] ; 1                 ; 6       ;
; SW[0]                                                    ;                   ;         ;
;      - JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[0] ; 0                 ; 6       ;
+----------------------------------------------------------+-------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                                                                                                                                                                                                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
; CLOCK_50                                                                                                                                                                                                                                                                                            ; PIN_G21            ; 219     ; Clock                      ; yes    ; Global Clock         ; GCLK9            ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|always0~1                                                                                                                                                                                                                                                       ; LCCOMB_X7_Y27_N30  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[2]~2                                                                                                                                                                            ; LCCOMB_X11_Y25_N30 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~0                                                                                                                                                                               ; LCCOMB_X14_Y26_N30 ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[4]~26                                                                                                                                                                           ; LCCOMB_X12_Y27_N14 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]~18                                                                                                                                                                           ; LCCOMB_X12_Y27_N6  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~3                                                                                                                                                                       ; LCCOMB_X11_Y26_N22 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~7                                                                                                                                                                           ; LCCOMB_X11_Y25_N2  ; 7       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT                                                                                                                                                                    ; FF_X12_Y25_N17     ; 26      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.WRITE_WAIT                                                                                                                                                                        ; FF_X11_Y26_N7      ; 13      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[0]~0                                                                                                                                                                          ; LCCOMB_X10_Y27_N0  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_ready                                                                                                                                                                                                           ; LCCOMB_X14_Y25_N28 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|write                                                                                                                                                                                                                        ; LCCOMB_X23_Y25_N10 ; 8       ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|always2~0                                                                                                                                                                                                         ; LCCOMB_X14_Y25_N24 ; 7       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_channel[7]~2                                                                                                                                                                                                  ; LCCOMB_X14_Y25_N12 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0                                        ; FF_X26_Y24_N15     ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full1~0                                      ; LCCOMB_X26_Y24_N2  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data                                                                             ; LCCOMB_X21_Y24_N2  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0                              ; LCCOMB_X27_Y25_N8  ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0                                                                                       ; LCCOMB_X23_Y19_N22 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~2                                                                                       ; LCCOMB_X24_Y19_N28 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid                                            ; LCCOMB_X24_Y21_N4  ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|virtual_state_sdr~0 ; LCCOMB_X24_Y19_N24 ; 46      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6]                                ; FF_X26_Y19_N17     ; 1       ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]~13                                                                        ; LCCOMB_X24_Y20_N0  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[4]~12                                                                        ; LCCOMB_X24_Y20_N6  ; 8       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n                                                                             ; FF_X24_Y19_N23     ; 8       ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~2                                                                                 ; LCCOMB_X23_Y19_N12 ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0                                                                                 ; LCCOMB_X23_Y20_N26 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~36                                                                               ; LCCOMB_X23_Y19_N14 ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1                                                                                   ; LCCOMB_X23_Y19_N26 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~11                                                                                   ; LCCOMB_X24_Y19_N4  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[14]~3                                                                                 ; LCCOMB_X23_Y20_N20 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~3                                                                      ; LCCOMB_X24_Y23_N2  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~2                                                                     ; LCCOMB_X26_Y21_N26 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0                                                                     ; LCCOMB_X24_Y21_N8  ; 9       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0                                                                                     ; LCCOMB_X24_Y19_N8  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~4                                                                         ; LCCOMB_X26_Y20_N2  ; 8       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1                                                                      ; LCCOMB_X26_Y22_N4  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]~1                                                                           ; LCCOMB_X24_Y21_N0  ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state~11                                                                                   ; LCCOMB_X26_Y20_N22 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~44                                                                  ; LCCOMB_X23_Y22_N20 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[3]~43                                                                  ; LCCOMB_X26_Y22_N0  ; 20      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~3                                                       ; LCCOMB_X23_Y21_N2  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1                                                                     ; LCCOMB_X24_Y23_N4  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~1                                                                          ; LCCOMB_X23_Y21_N4  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~19                                                                                  ; LCCOMB_X23_Y20_N28 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1]                                                                                         ; FF_X26_Y24_N1      ; 41      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~1                                                                                                                                                                                                        ; LCCOMB_X21_Y24_N30 ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                                                                                               ; FF_X20_Y5_N9       ; 151     ; Async. clear               ; yes    ; Global Clock         ; GCLK16           ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0                                                                                                                                         ; LCCOMB_X6_Y26_N6   ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~2                                                                                                                                        ; LCCOMB_X6_Y26_N28  ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|save_dest_id~0                                                                                                                                                                                  ; LCCOMB_X6_Y27_N6   ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                                                                                                                         ; FF_X19_Y28_N1      ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK14           ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                                                                                                                                                                                                        ; JTAG_X1_Y15_N0     ; 296     ; Clock                      ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                                                        ; JTAG_X1_Y15_N0     ; 23      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                               ; FF_X20_Y20_N5      ; 13      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0                                                                                                                                                                                                                    ; LCCOMB_X17_Y21_N4  ; 4       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena                                                                                                                                                                                                                      ; LCCOMB_X17_Y21_N20 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0                                                                                                                                                                                                                    ; LCCOMB_X19_Y21_N14 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~1                                                                                                                                                                                                       ; LCCOMB_X17_Y20_N26 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0                                                                                                                                                                                                      ; LCCOMB_X17_Y20_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~0                                                                                                                                                                                                                       ; LCCOMB_X19_Y21_N2  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]~4                                                                                                                                                                                                                         ; LCCOMB_X20_Y21_N26 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~12                                                                                                                                                                                                                  ; LCCOMB_X20_Y20_N22 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~19                                                                                                                                                                                                                  ; LCCOMB_X19_Y21_N22 ; 5       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]~14                                                                                                                                                                                                 ; LCCOMB_X20_Y20_N10 ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~22                                                                                                                                                                                            ; LCCOMB_X21_Y20_N30 ; 5       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~23                                                                                                                                                                                            ; LCCOMB_X20_Y20_N28 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                    ; FF_X20_Y20_N31     ; 15      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                   ; FF_X21_Y18_N1      ; 12      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                    ; FF_X20_Y20_N19     ; 29      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                    ; FF_X19_Y21_N17     ; 12      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0                                                                                                                                                                                                             ; LCCOMB_X21_Y18_N18 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                   ; FF_X21_Y19_N25     ; 41      ; Async. clear, Clock enable ; no     ; --                   ; --               ; --                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                                                                                                  ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; CLOCK_50                                                                                                                                                              ; PIN_G21        ; 219     ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X20_Y5_N9   ; 151     ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                           ; FF_X19_Y28_N1  ; 55      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
; altera_internal_jtag~TCKUTAP                                                                                                                                          ; JTAG_X1_Y15_N0 ; 296     ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                                                                                                                                                                                                               ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                                                                                                                                                                                                                ; Fan-Out ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                                                                                                    ; 46      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|virtual_state_sdr~0 ; 46      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                                                                                                   ; 41      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1]                                                                                         ; 41      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_WRITE_DATA                                                                                                                                                                    ; 30      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                                                                                                    ; 29      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                                                                                                      ; 28      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_WAIT                                                                                                                                                                    ; 26      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|always2~0                                                                                       ; 25      ;
; altera_internal_jtag~TMSUTAP                                                                                                                                                                                                                                                                        ; 23      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|enable                                                                                                                                                                                  ; 22      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[3]~43                                                                  ; 20      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~3                                                       ; 19      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~0                                                       ; 19      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]~44                                                                  ; 19      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0                                        ; 19      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_HEADER                                                                            ; 18      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[2]                                                                                                                                                                              ; 18      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[3]                                                                                                                                                                              ; 18      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR4                                                                                                                                                                         ; 17      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~0                                                                                       ; 17      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_READ_DATA                                                                         ; 17      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|always1~0                                                                                                                                                                               ; 16      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                                                                                                    ; 15      ;
; altera_internal_jtag~TDIUTAP                                                                                                                                                                                                                                                                        ; 14      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_CMD_WAIT                                                                                                                                                                     ; 14      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                                                                                               ; 13      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                                                                                                           ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]~1                                                                           ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|read_latency_shift_reg[0]                                                                                                                                                            ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|read_latency_shift_reg[0]                                                                                                                                                           ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.WRITE_WAIT                                                                                                                                                                        ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal17~0                                                                                       ; 13      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[4]                                                                                                                                                                              ; 13      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                                                                                                    ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                                                                                                         ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                                                                                                   ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[14]~3                                                                                 ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_WRITE_DATA                                                                       ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~1                                                                                                                                                                           ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_startofpacket                                                                                                                                                                                                 ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[4]                                                                                                                                                                              ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~1                                                                                                                                                                                                        ; 12      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|write                                                                                                                                                                                   ; 12      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                                                                                                         ; 11      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                                                                                                         ; 11      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~2                                                                                                                                                                           ; 11      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_SEND_ISSUE                                                                                                                                                                   ; 11      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.RETURN_PACKET                                                                                                                                                                     ; 11      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]                                                                                                                                                                                                                     ; 10      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]                                                                                                                                                                         ; 10      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|out_data~2                                         ; 10      ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]                                                                                                                                                                                                                     ; 9       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]                                                                                                                                                                                                                     ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid                                            ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]~0                                                                     ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|sync_control_signal~0                              ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_BYPASS                                                                           ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready                                                                                                                                                                                                          ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|virtual_state_cdr   ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~2                                                                         ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Equal6~0                                                                                                                                                                                ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~2                                                                                                                                                                                                        ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|av_waitrequest                                                                                                                                  ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                                                           ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]~2                                                                                 ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]                                                                                                                                          ; 9       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[0]                                                                                                                                                                                                               ; 9       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                                                                                                           ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]                                                                                                                                                                                                                     ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_channel[7]~2                                                                                                                                                                                                  ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[0]~11                                                                                   ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[0]~36                                                                               ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[2]                                                                            ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n                                                                             ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]~0                                                                                 ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]~13                                                                        ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[4]~12                                                                        ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|take_in_data                                                                             ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[0]                                                                                                                                                                                                                    ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[0]                                                                                                                                                                                                                    ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|write                                                                                                                                                                                                                        ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]~0                                                                                     ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[4]~26                                                                                                                                                                           ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]~18                                                                                                                                                                           ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|av_readdatavalid~0                                                                                                                              ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]~4                                                                         ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full1~0                                      ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|writedata[0]~0                                                                                                                                                                          ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full1                                        ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|always0~1                                                                                                                                                                                                                                                       ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[1]                                                                                                                                                                                                               ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[2]                                                                                                                                                                                                               ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[3]                                                                                                                                                                                                               ; 8       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[1]                                                                                                                                                                         ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                                                                                                                                                   ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                                                                                                           ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                                                                                                           ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]                                                                                                                                                                                                                     ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[1]                                                                            ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[1]                                                                                                                                                                                                                    ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[1]                                                                                                                                                                                                                    ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~7                                                                                                                                                                           ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~3                                                                                                                                                                           ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_DATA_WAIT                                                                                                                                                                    ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[1]                                                                             ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]                                                                             ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[2]                                                                             ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read                                                                                                                                                                                    ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|always2~0                                                                                                                                                                                                         ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_esc                                                                                                                                                                                                      ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~6                                                                                                                                                                                                        ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_startofpacket                                                                                                                                                                       ; 7       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal16~0                                                                                       ; 7       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                                                                                               ; 6       ;
; ~GND                                                                                                                                                                                                                                                                                                ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[7]~1                                                                                                                                                                                                     ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_HEADER_1                                                                         ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_valid                                                                                                                                                                                                           ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[7]~0                                                                                                                                                                                                     ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~1                                                                     ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_endofpacket                                                                                                                                                                                                   ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal1~0                                                                                        ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]                                                                        ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]                                                                       ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid                                                                             ; 6       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[4]                                                                                                                                                                                                               ; 6       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~23                                                                                                                                                                                            ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~22                                                                                                                                                                                            ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~19                                                                                                                                                                                                                  ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~12                                                                                                                                                                                                                  ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0                                                                                                                                                                                                                    ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                                                                                                               ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                                                                                               ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                                                                                               ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                                                                                                           ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]                                                                            ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[4]                                                                                                                                                                                                                    ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|read~0                                                                                                                                                                                                                       ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[2]                                                                                                                                                                                                                    ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[2]                                                                                                                                                                                                                    ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~17                                                                                  ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR1                                                                                                                                                                         ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.0000                                                                                                                                                                              ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|last_trans                                                                                                                                                                              ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Equal2~1                                                                                                                                                                                ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_ready                                                                                                                                                                                                           ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~9                                                                                ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_channel                                                                                                                                                                                                  ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0                                                                                                                                                                              ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_valid                                                                                                                                                                                                                    ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~3                                                                                                                                                                                                        ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_sop                                                                                                                                                                                                          ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_toggle                                                                           ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~0                                                                                                                                                                                                        ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[1]                                                                        ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[1]                                                                       ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~5                                                                                   ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[0]                                                                           ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[1]~1                                                                                 ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|wait_latency_counter[0]                                                                                                                                                             ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|wait_latency_counter[1]                                                                                                                                                             ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[6]                                                                                                                                                                                                               ; 5       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[7]                                                                                                                                                                                                               ; 5       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]~14                                                                                                                                                                                                 ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~1                                                                                                                                                                                                       ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0                                                                                                                                                                                                      ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal                                                                                                                                                                                                  ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena                                                                                                                                                                                                                      ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0                                                                                                                                                                                                                    ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]~19                                                                                                                                                                                                                 ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                                                                                                       ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~0                                                                                                                                                                                                                       ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg_proc~0                                                                                                                                                                                                                  ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~37                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~25                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~11                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[7]                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]~3                                                                      ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add1~1                                                                                                                                                                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[3]                                                                                                                                                                                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[4]                                                                                                                                                                                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[3]                                                                                                                                                                                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~19                                                                                  ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[2]                                                                        ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[0]                                                                        ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_channel~0                                                                                                                                                                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_channel_char                                                                                                                                                                                                 ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector0~3                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|save_dest_id~0                                                                                                                                                                                  ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|WideOr0~3                                                                                                                                                                     ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR2                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_SIZE2                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_SIZE1                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.READ_ASSERT                                                                                                                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_ADDR3                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]~2                                                                     ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_valid~0                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~14                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state.ST_PADDED                                                                            ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state~8                                                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~12                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[7]                                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state.ST_HEADER_2                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready                                                                      ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_valid~1                                                                                                                                                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~5                                                                                                                                                                                                        ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|in_ready~4                                                                                                                                                                                                        ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_channel                                                                                                                                                                                                      ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_valid                                                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[6]                                   ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_endofpacket                                                                                                                                                                         ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Equal10~4                                                                                                                                                                               ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|hold_waitrequest                                                                                                                                ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[2]                                                                        ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[2]                                                                       ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[2]                                                                           ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[1]                                                                           ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[1]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[2]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[3]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[0]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[4]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[5]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[6]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[7]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[9]                                                                                                                                                                              ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[10]                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[11]                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[12]                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[13]                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[14]                                                                                                                                                                             ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[15]                                                                                                                                                                             ; 4       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                                                                                                  ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]~4                                                                                                                                                                                                                         ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                                                                                                       ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0                                                                                                                                                                                                             ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                                                                                                        ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                                                                                                        ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                                                                                                   ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                                                                                                    ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                                                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~1                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2                                                                                 ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[0]~1                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[1]                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[6]                                                                                  ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|out_data~4                                         ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|received_esc                                         ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[2]                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[1]                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|Equal0~0                                             ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[0]                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[14]~2                                                                                 ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|rd_ptr[5]                                                                                                                                                                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[5]                                                                                                                                                                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_length[0]~0                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Add1~0                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[15]                                                                                   ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[14]                                                                                   ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]~0                                                                           ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[3]                                                                        ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[1]                                                                        ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|Equal0~1                                                                                                                                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|wait_latency_counter[0]~0                                                                                                                                                            ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0                                                                                                                                         ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                           ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_EXTRA                                                                                                                                                                         ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~0                                                                                                                                                                           ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|WideOr12~1                                                                                                                                                                              ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[0]                                                                                  ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[0]~1                                                                      ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[7]~10                                                                               ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Selector42~1                                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter~12                                                                           ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[6]                                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[5]                                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[4]                                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal6~0                                                                                        ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[3]                                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_toggle_flopped                                                                  ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_data[5]~0                                                                                                                                                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]                                                                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|read_latency_shift_reg~0                                                                                                                                                            ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector81~0                                                                                                                                                                            ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|Equal0~0                                                                                                                                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[2]~2                                                                                                                                                                            ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[7]                                                                                                                                                                             ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_esc                                                                                                                                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[0]                                                                                                                                                                                                 ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_valid                                                                                                                                                                               ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_eop                                                                                                                                                                                                          ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|has_pending_responses                                                                                                                                                                           ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|WideOr0~2                                                                                                                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|wait_latency_counter[0]                                                                                                                                                              ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|wait_latency_counter[1]                                                                                                                                                              ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|WideOr12~0                                                                                                                                                                              ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[7]~8                                                                                ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal3~5                                                                                        ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_valid                                                                                 ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[3]                                                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter|received_esc                                       ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[0]                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|out_payload[5]                                                                                                                                                                                                               ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[10]                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[9]                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[8]                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[14]                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[13]                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[12]                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[11]                                                                    ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[8]                                                                           ; 3       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                                                                                                         ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                                                                                                         ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~7                                                                                                                                                                                                     ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                                                                                                         ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~0                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3                                                                                                                                                                                                                         ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~1                                                                                                                                                                                                                              ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~0                                                                                                                                                                                                                              ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                                                                                                                                        ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1                                                                                                                                                                                                                       ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~1                                                                                                                                                                                                                                 ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~0                                                                                                                                                                                                                                 ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9]                                                                                                                                                                                                    ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                                                                                                  ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                                                                                                   ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~14                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[8]                                                                                      ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[18]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[17]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[16]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[15]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[14]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[13]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[12]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[11]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[10]                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[9]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[8]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[7]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[6]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[5]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[4]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[3]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[2]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[1]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[3]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[2]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[6]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[5]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[7]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[4]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[2]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid~3                                          ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid~2                                          ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[5]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[4]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[6]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_data[3]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_remover_sink_valid                                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_to_sample_div2                                                                            ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~4                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~3                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~2                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~1                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~0                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[6]       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~21                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal6~1                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|empty                                                                                                                                                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_valid~2                                                                                                                                                                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem~1                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem~1                                                                                                                                                 ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem~0                                                                                                                                                 ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~2                                                                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem~0                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|read_latency_shift_reg~0                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~66                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[5]~5                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[4]~4                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[3]~3                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add1~0                                                                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[2]~2                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[1]~1                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rd_ptr[0]~0                                                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|full                                                                                                                                                                                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_valid                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[6]                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[5]                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[13]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[12]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[11]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[10]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[9]                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[8]                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[7]                                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[7]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[6]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[5]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[4]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|virtual_state_udr   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter~2                                                                         ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal14~2                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[3]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|Equal2~0                                                                                                                                                                                                          ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]~5                                                                                                                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|WideOr14~0                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|first_trans                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~25                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~24                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~23                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~22                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~21                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~20                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~19                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]~17                                                                                                                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter~16                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~61                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|response_sink_accepted~0                                                                                                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|pending_response_count[0]                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|wait_latency_counter[0]~1                                                                                                                                                            ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~56                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~53                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~52                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~51                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~48                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~46                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~3                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~43                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[0]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[1]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[3]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[5]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[6]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[2]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[1]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[9]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[8]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[7]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[6]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[5]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[4]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length[3]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_valid~1                                                                               ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state~11                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~11                                                                               ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[0]                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[1]                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|offset[2]                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_valid_internal                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|dreg[1]                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid~2                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_1                                                                                 ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_all_valid~1                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[4]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[3]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[5]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[7]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[6]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[1]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[2]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_buffer[0]                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[2]                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[2]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|wait_latency_counter[1]~2                                                                                                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_waitrequest_generated~0                                                                                                                                                          ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|wait_latency_counter[1]~1                                                                                                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|suppress_change_dest_id~1                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~40                                                                                                                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[3]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[4]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[5]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[1]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[2]                                                                                                                                                                             ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|suppress_change_dest_id~0                                                                                                                                                                       ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|last_dest_id[0]                                                                                                                                                                                 ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|WideOr0~0                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_waitrequest_generated~0                                                                                                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|command[2]                                                                                                                                                                              ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal3~3                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal3~2                                                                                        ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]~7                                                                                ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[1]                                                                                  ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~1                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[7]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[6]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[5]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~0                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[4]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[3]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[4]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[3]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[5]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[7]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[6]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[1]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|data1[2]                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_loopback~0                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]~1                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[1]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_loopback                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[0]                                                                                   ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[7]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[6]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[5]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[4]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[3]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[2]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[1]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|data_out[0]                                                                                                                                                                                                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[6]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[5]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[4]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[3]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[7]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[0]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[2]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[1]                                                                           ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[0]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[18]                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[17]                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[16]                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[15]                                                                    ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[7]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[6]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[5]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[4]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[3]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[2]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[1]                                                                     ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|din_s1~feeder                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sensor~feeder                                                                             ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|din_s1~feeder                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder                                                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|hold_waitrequest~feeder                                                                                                                         ; 1       ;
; altera_reserved_tdi~input                                                                                                                                                                                                                                                                           ; 1       ;
; altera_reserved_tck~input                                                                                                                                                                                                                                                                           ; 1       ;
; altera_reserved_tms~input                                                                                                                                                                                                                                                                           ; 1       ;
; SW[0]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[3]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[4]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[6]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[7]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[5]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[1]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[2]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[9]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; SW[8]~input                                                                                                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~_wirecell                                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]~1                                                                                                                                                                                                                      ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]~0                                                                                                                                                                                                                      ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~24                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~23                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~22                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~21                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~20                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~15                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~14                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~13                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~12                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~11                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg~3                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                                                                                                        ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~15                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~10                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~9                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~8                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3]                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg~2                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                                                                                                        ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt~2                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt~1                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~6                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~5                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2]                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg~1                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]~4                                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal3~0                                                                                                                                                                                                                              ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                                                                                                        ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~11                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt~0                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]~3                                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]~2                                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg                                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~2                                                                                                                                                                                                                              ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]~1                                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]~0                                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg~8                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg~7                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg~6                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~4                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1]                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg~5                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg~0                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg~2                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg~0                                                                                                                                                                                                                      ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]~18                                                                                                                                                                                                                 ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                                                                                                        ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~17                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~16                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~12                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~11                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~10                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~9                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~8                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~7                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~6                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~5                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~4                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~3                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~2                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0                                                                                                                                                                                                     ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal1~0                                                                                                                                                                                                                              ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg_proc~0                                                                                                                                                                                                                        ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~2                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0                                                                                                                                                                                                                       ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~1                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~0                                                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~5                                                                                                                                                                                                                                 ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~4                                                                                                                                                                                                                                 ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~3                                                                                                                                                                                                                                 ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo~2                                                                                                                                                                                                                                 ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~20                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]~3                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]~19                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]~18                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]~17                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]~16                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~14                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]~13                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~12                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]~11                                                                                                                                                                                            ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3]                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]~2                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2]                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~1                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4]~17                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]~16                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3]~15                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]~14                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2]~13                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]~10                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1]~9                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~8                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~7                                                                                                                                                                                                                   ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]~1                                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]~0                                                                                                                                                                                                                         ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]                                                                                                                                                                                                                    ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]~0                                                                                                                                                                                                                  ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                                                                                                    ; 1       ;
; altera_internal_jtag~TDO                                                                                                                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_to_sample_div2~0                                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|wr_ptr[0]~0                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|last_channel[1]~0                                                                                                                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~22                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter~7                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state.GET_EXTRA~2                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_1~3                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~7                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_sop~3                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_eop~2                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]~6                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[2]~3                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Selector41~4                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|din_s1                                 ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[0]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_valid_buffer                                                                             ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[1]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|din_s1        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[2]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[0]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[3]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2~2                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2~1                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_2~0                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[1]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[8]~10                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[4]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|din_s1                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~35                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~34                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~33                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~32                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~31                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~30                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~29                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~28                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~27                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~26                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~24                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~23                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~22                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~21                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~20                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~19                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~18                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~17                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~16                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~15                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~13                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~12                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~10                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~9                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~8                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~7                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~6                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~5                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~4                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]~2                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter~1                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[2]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~9                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[7]~35                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[7]~34                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[0]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[5]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[0]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter~3                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Add3~0                                                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter~2                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter~0                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~5                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~4                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~3                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~2                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~1                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal13~0                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[3]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~8                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[7]                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~33                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~32                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[7]                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[0]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[0]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6]                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[1]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|received_esc~0                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_valid                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_in[1]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[4]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~7                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[6]                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~31                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~30                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~29                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~28                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~27                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]~26                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector80~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector80~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector80~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|src_data[0]                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[0]                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[0]                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sensor                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_data[5]~0                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[2]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|out_valid~4                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover|Equal0~1                                             ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[5]       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~6                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[5]                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~25                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~24                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~23                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[5]                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~11                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~10                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~9                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~8                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~7                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~6                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~5                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~4                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~3                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data~2                                                                                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[0]                                                                                                                                                                             ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|din_s1                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_empty~0                                                                                                                                                                                                                 ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[1]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[2]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[7]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[5]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[6]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[3]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[3]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[4]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[6]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[7]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[5]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[1]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|read_mux_out[2]                                                                                                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[3]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[4]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Add0~5                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|sink_data_buffer[0]                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_full~4                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_full~3                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_full~2                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_full~1                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|next_full~0                                                                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|edge_detector_register                             ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~5                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[4]                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~22                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~20                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[4]                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~9                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[8]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~8                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~7                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~6                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|din_s1                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~21                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter~6                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter~5                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter~4                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~20                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|Equal6~2                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[4]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[3]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[5]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[7]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[6]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[1]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[2]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|din_s1                                                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[0]                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer|din_s1                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|dreg[0]                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~5                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_valid~3                                                                                                                                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Equal0~2                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Equal0~1                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|Equal0~0                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_valid~1                                                                                                                                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_valid~0                                                                                                                                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[1]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[2]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[7]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[5]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[6]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[3]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[3]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[3]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[4]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[4]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[6]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[6]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[7]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[7]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[5]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[5]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[1]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[1]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout|readdata[2]                                                                                                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[2]                                                                                                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|sent_channel_char~0                                                                                                                                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector38~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[4]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][103]                                                                                                                                          ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][103]                                                                                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|pending_response_count[0]~0                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|WideOr0~4                                                                                                                                                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]~3                                                                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~78                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~77                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~76                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~75                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~74                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~73                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70]                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70]                                                                                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~72                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~71                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~70                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~69                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~68                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~67                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~65                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~64                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[4]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~63                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_startofpacket~1                                                                                                                                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_startofpacket~0                                                                                                                                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector39~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[0]                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info~4                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[3]                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in[4]                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~19                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~18                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out~17                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state~15                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|out_data_toggle_flopped~0                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~18                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~16                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~15                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~14                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_length[0]~2                                                                           ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decode_header_1~2                                                                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[4]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[3]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[5]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[7]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[6]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[1]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[2]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~7                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~6                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~5                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~4                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~3                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|idle_inserter_source_ready~2                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[0]                                                                                         ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full0~0                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage|full1~2                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|in_data_buffer[0]                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|din_s1                                     ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer|dreg[0]                               ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug~3                                                                                      ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|dreg[1]                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control~4                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|read_latency_shift_reg~1                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0]~1                                                                                                                                        ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector83~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector83~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_endofpacket~1                                                                                                                                                                                                 ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|out_endofpacket~0                                                                                                                                                                                                 ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_channel~1                                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_channel~0                                                                                                                                                                                                ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0~4                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0~3                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|in_ready_0~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_esc~0                                                                                                                                                                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector77~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector77~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector77~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|src_data[3]                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[3]                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[3]                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector76~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector76~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector76~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|src_data[4]                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[4]                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[4]                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector74~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector74~1                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector74~0                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|src_data[6]                                                                                                                                                                       ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[6]                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[6]                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~6                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~5                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~4                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~3                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector73~2                                                                                                                                                                            ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[7]                                                                                                                                                                  ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[7]                                                                                                                                                                   ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|Selector75~2                                                                                                                                                                            ; 1       ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+
; Name                                                                                                                                  ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64           ; 8            ; 64           ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 512  ; 64                          ; 8                           ; 64                          ; 8                           ; 512                 ; 1    ; None ; M9K_X25_Y25_N0 ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------+----------------------+-----------------+-----------------+---------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 943 / 47,787 ( 2 % )   ;
; C16 interconnects     ; 0 / 1,804 ( 0 % )      ;
; C4 interconnects      ; 370 / 31,272 ( 1 % )   ;
; Direct links          ; 217 / 47,787 ( < 1 % ) ;
; Global clocks         ; 4 / 20 ( 20 % )        ;
; Local interconnects   ; 614 / 15,408 ( 4 % )   ;
; R24 interconnects     ; 9 / 1,775 ( < 1 % )    ;
; R4 interconnects      ; 491 / 41,310 ( 1 % )   ;
+-----------------------+------------------------+


+----------------------------------------------------------------------------+
; LAB Logic Elements                                                         ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 12.61) ; Number of LABs  (Total = 74) ;
+---------------------------------------------+------------------------------+
; 1                                           ; 1                            ;
; 2                                           ; 2                            ;
; 3                                           ; 5                            ;
; 4                                           ; 2                            ;
; 5                                           ; 0                            ;
; 6                                           ; 1                            ;
; 7                                           ; 2                            ;
; 8                                           ; 1                            ;
; 9                                           ; 1                            ;
; 10                                          ; 2                            ;
; 11                                          ; 3                            ;
; 12                                          ; 3                            ;
; 13                                          ; 5                            ;
; 14                                          ; 5                            ;
; 15                                          ; 12                           ;
; 16                                          ; 29                           ;
+---------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 2.04) ; Number of LABs  (Total = 74) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 33                           ;
; 1 Clock                            ; 66                           ;
; 1 Clock enable                     ; 24                           ;
; 1 Sync. clear                      ; 2                            ;
; 1 Sync. load                       ; 6                            ;
; 2 Async. clears                    ; 5                            ;
; 2 Clock enables                    ; 11                           ;
; 2 Clocks                           ; 4                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 18.84) ; Number of LABs  (Total = 74) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 1                            ;
; 1                                            ; 0                            ;
; 2                                            ; 1                            ;
; 3                                            ; 0                            ;
; 4                                            ; 2                            ;
; 5                                            ; 0                            ;
; 6                                            ; 4                            ;
; 7                                            ; 0                            ;
; 8                                            ; 2                            ;
; 9                                            ; 1                            ;
; 10                                           ; 0                            ;
; 11                                           ; 2                            ;
; 12                                           ; 1                            ;
; 13                                           ; 0                            ;
; 14                                           ; 1                            ;
; 15                                           ; 2                            ;
; 16                                           ; 3                            ;
; 17                                           ; 6                            ;
; 18                                           ; 3                            ;
; 19                                           ; 1                            ;
; 20                                           ; 6                            ;
; 21                                           ; 5                            ;
; 22                                           ; 9                            ;
; 23                                           ; 3                            ;
; 24                                           ; 5                            ;
; 25                                           ; 6                            ;
; 26                                           ; 4                            ;
; 27                                           ; 3                            ;
; 28                                           ; 1                            ;
; 29                                           ; 1                            ;
; 30                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 6.78) ; Number of LABs  (Total = 74) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 1                            ;
; 1                                               ; 11                           ;
; 2                                               ; 5                            ;
; 3                                               ; 5                            ;
; 4                                               ; 4                            ;
; 5                                               ; 5                            ;
; 6                                               ; 3                            ;
; 7                                               ; 8                            ;
; 8                                               ; 7                            ;
; 9                                               ; 5                            ;
; 10                                              ; 4                            ;
; 11                                              ; 7                            ;
; 12                                              ; 4                            ;
; 13                                              ; 1                            ;
; 14                                              ; 0                            ;
; 15                                              ; 0                            ;
; 16                                              ; 2                            ;
; 17                                              ; 1                            ;
; 18                                              ; 0                            ;
; 19                                              ; 0                            ;
; 20                                              ; 0                            ;
; 21                                              ; 0                            ;
; 22                                              ; 0                            ;
; 23                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                         ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 12.03) ; Number of LABs  (Total = 74) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 2                            ;
; 2                                            ; 3                            ;
; 3                                            ; 6                            ;
; 4                                            ; 3                            ;
; 5                                            ; 1                            ;
; 6                                            ; 1                            ;
; 7                                            ; 1                            ;
; 8                                            ; 4                            ;
; 9                                            ; 4                            ;
; 10                                           ; 4                            ;
; 11                                           ; 8                            ;
; 12                                           ; 5                            ;
; 13                                           ; 4                            ;
; 14                                           ; 1                            ;
; 15                                           ; 3                            ;
; 16                                           ; 4                            ;
; 17                                           ; 3                            ;
; 18                                           ; 3                            ;
; 19                                           ; 4                            ;
; 20                                           ; 2                            ;
; 21                                           ; 1                            ;
; 22                                           ; 0                            ;
; 23                                           ; 1                            ;
; 24                                           ; 1                            ;
; 25                                           ; 0                            ;
; 26                                           ; 1                            ;
; 27                                           ; 0                            ;
; 28                                           ; 1                            ;
; 29                                           ; 0                            ;
; 30                                           ; 2                            ;
+----------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 12    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 18    ;
+----------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules           ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass          ; 21           ; 0            ; 21           ; 0            ; 0            ; 25        ; 21           ; 0            ; 25        ; 25        ; 0            ; 10           ; 0            ; 0            ; 11           ; 0            ; 10           ; 11           ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 25        ; 0            ; 0            ;
; Total Unchecked     ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable  ; 4            ; 25           ; 4            ; 25           ; 25           ; 0         ; 4            ; 25           ; 0         ; 0         ; 25           ; 15           ; 25           ; 25           ; 14           ; 25           ; 15           ; 14           ; 25           ; 25           ; 25           ; 15           ; 25           ; 25           ; 25           ; 25           ; 25           ; 0         ; 25           ; 25           ;
; Total Fail          ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; LEDG[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[3]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[4]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[5]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[6]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[7]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[8]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; LEDG[9]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[8]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[9]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; CLOCK_50            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[2]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[1]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[5]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[7]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[6]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[4]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[3]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; SW[0]               ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+---------------------------------------------------------------------------------------------+
; Fitter Device Options                                                                       ;
+------------------------------------------------------------------+--------------------------+
; Option                                                           ; Setting                  ;
+------------------------------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
; Enable INIT_DONE output                                          ; Off                      ;
; Configuration scheme                                             ; Active Serial            ;
; Error detection CRC                                              ; Off                      ;
; Enable open drain on CRC_ERROR pin                               ; Off                      ;
; Enable input tri-state on active configuration pins in user mode ; Off                      ;
; Configuration Voltage Level                                      ; Auto                     ;
; Force Configuration Voltage Level                                ; Off                      ;
; nCEO                                                             ; As output driving ground ;
; Data[0]                                                          ; As input tri-stated      ;
; Data[1]/ASDO                                                     ; As input tri-stated      ;
; Data[7..2]                                                       ; Unreserved               ;
; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
; Other Active Parallel pins                                       ; Unreserved               ;
; DCLK                                                             ; As output driving ground ;
; Base pin-out file on sameframe device                            ; Off                      ;
+------------------------------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (119006): Selected device EP3C16F484C6 for design "top"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device EP3C40F484C6 is compatible
    Info (176445): Device EP3C55F484C6 is compatible
    Info (176445): Device EP3C80F484C6 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity altera_avalon_st_clock_crosser
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
        Info (332166): set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]
    Info (332165): Entity altera_std_synchronizer
        Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
    Info (332165): Entity sld_jtag_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'JTAG_MM/synthesis/submodules/altera_reset_controller.sdc'
Info (332104): Reading SDC File: 'JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.sdc'
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
    Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 1 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):  100.000 altera_reserved_tck
Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|din_s1
Info (176353): Automatically promoted node JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out 
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176218): Packed 8 registers into blocks of type EC
Warning (15705): Ignored locations or region assignments to the following nodes
    Warning (15706): Node "BUTTON [0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "BUTTON [1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "BUTTON [2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_BA_0" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_BA_1" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design
    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX0_D[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX1_D[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX2_D[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[4]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[5]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "HEX3_D[6]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
    Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 1% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 0.47 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info (144001): Generated suppressed messages file d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 96 warnings
    Info: Peak virtual memory: 1131 megabytes
    Info: Processing ended: Tue Jun 09 09:53:51 2015
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:10


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.fit.smsg.


