Analysis & Synthesis report for top
Tue Jun 09 09:53:40 2015
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state
 11. State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state
 12. State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state
 13. Registers Protected by Synthesis
 14. Registers Removed During Synthesis
 15. Removed Registers Triggering Further Register Optimizations
 16. General Register Statistics
 17. Inverted Register Statistics
 18. Registers Packed Into Inferred Megafunctions
 19. Multiplexer Restructuring Statistics (Restructuring Performed)
 20. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer
 21. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming
 22. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer
 23. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer
 24. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer
 25. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer
 26. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer
 27. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer
 28. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser
 29. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer
 30. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
 31. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
 32. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux
 33. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux
 34. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux_001
 35. Source assignments for JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
 36. Source assignments for JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
 37. Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated
 38. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0
 39. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master
 40. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming
 41. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer
 42. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming
 43. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer
 44. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer
 45. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer
 46. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer
 47. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node
 48. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component
 49. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser
 50. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer
 51. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer
 52. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage
 53. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser
 54. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser
 55. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer
 56. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo
 57. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p
 58. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b
 59. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto
 60. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m
 61. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller
 62. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
 63. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
 64. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator
 65. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator
 66. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator
 67. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent
 68. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent
 69. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor
 70. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
 71. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent
 72. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor
 73. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
 74. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode
 75. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode
 76. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router_001|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode
 77. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter
 78. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb
 79. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder
 80. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller
 81. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1
 82. Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1
 83. Parameter Settings for Inferred Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0
 84. altsyncram Parameter Settings by Entity Instance
 85. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller"
 86. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
 87. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode"
 88. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode"
 89. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo"
 90. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent"
 91. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo"
 92. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent"
 93. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent"
 94. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator"
 95. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator"
 96. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator"
 97. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1"
 98. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller"
 99. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo"
100. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser"
101. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter"
102. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover"
103. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component"
104. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node"
105. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer"
106. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer"
107. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer"
108. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer"
109. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer"
110. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master"
111. Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0"
112. Port Connectivity Checks: "JTAG_MM:U_jtag_mm"
113. Elapsed Time Per Partition
114. Analysis & Synthesis Messages
115. Analysis & Synthesis Suppressed Messages



----------------
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----------------
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+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Jun 09 09:53:40 2015       ;
; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name                      ; top                                         ;
; Top-level Entity Name              ; top                                         ;
; Family                             ; Cyclone III                                 ;
; Total logic elements               ; 992                                         ;
;     Total combinational functions  ; 781                                         ;
;     Dedicated logic registers      ; 522                                         ;
; Total registers                    ; 522                                         ;
; Total pins                         ; 21                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 512                                         ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C16F484C6       ;                    ;
; Top-level entity name                                                      ; top                ; top                ;
; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                               ;
+--------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path                                         ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                                                   ; Library ;
+--------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------+
; top.v                                                                    ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/top.v                                                                    ;         ;
; JTAG_MM/synthesis/JTAG_MM.v                                              ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/JTAG_MM.v                                              ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_reset_controller.v                   ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_controller.v                   ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v                 ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_reset_synchronizer.v                 ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v                 ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0.v                 ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv                 ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_arbitrator.sv                 ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv   ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_mux.sv   ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_demux.sv ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_rsp_xbar_demux.sv ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_mux.sv   ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_mux.sv   ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_demux.sv ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_cmd_xbar_demux.sv ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_traffic_limiter.sv            ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_traffic_limiter.sv            ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v                     ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_sc_fifo.v                     ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_pipeline_base.v            ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_pipeline_base.v            ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv      ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_id_router.sv      ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv    ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_mm_interconnect_0_addr_router.sv    ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv                ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_slave_agent.sv                ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_burst_uncompressor.sv         ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_burst_uncompressor.sv         ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv               ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_master_agent.sv               ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_slave_translator.sv           ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_slave_translator.sv           ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_merlin_master_translator.sv          ; yes             ; User SystemVerilog HDL File  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_merlin_master_translator.sv          ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_PIN.v                               ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_PIN.v                               ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_POUT.v                              ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_POUT.v                              ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v                          ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0.v                          ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_master_0_p2b_adapter.v              ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_p2b_adapter.v              ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v              ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_b2p_adapter.v              ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v           ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_packets_to_master.v           ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v         ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_packets_to_bytes.v         ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_bytes_to_packets.v         ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_bytes_to_packets.v         ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/JTAG_MM_master_0_timing_adt.v               ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/JTAG_MM_master_0_timing_adt.v               ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v           ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_jtag_interface.v           ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v                  ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_dc_streaming.v                  ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v                      ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_sld_node.v                      ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_jtag_streaming.v                     ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_jtag_streaming.v                     ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v            ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_clock_crosser.v            ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_idle_remover.v             ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_idle_remover.v             ; JTAG_MM ;
; JTAG_MM/synthesis/submodules/altera_avalon_st_idle_inserter.v            ; yes             ; User Verilog HDL File        ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/JTAG_MM/synthesis/submodules/altera_avalon_st_idle_inserter.v            ; JTAG_MM ;
; altera_std_synchronizer.v                                                ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/altera_std_synchronizer.v                                                       ;         ;
; sld_virtual_jtag_basic.v                                                 ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v                                                        ;         ;
; sld_hub.vhd                                                              ; yes             ; Encrypted Megafunction       ; c:/altera/13.1/quartus/libraries/megafunctions/sld_hub.vhd                                                                     ;         ;
; sld_jtag_hub.vhd                                                         ; yes             ; Encrypted Megafunction       ; c:/altera/13.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd                                                                ;         ;
; sld_rom_sr.vhd                                                           ; yes             ; Encrypted Megafunction       ; c:/altera/13.1/quartus/libraries/megafunctions/sld_rom_sr.vhd                                                                  ;         ;
; altsyncram.tdf                                                           ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf                                                                  ;         ;
; stratix_ram_block.inc                                                    ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc                                                           ;         ;
; lpm_mux.inc                                                              ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc                                                                     ;         ;
; lpm_decode.inc                                                           ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc                                                                  ;         ;
; aglobal131.inc                                                           ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                                                  ;         ;
; a_rdenreg.inc                                                            ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc                                                                   ;         ;
; altrom.inc                                                               ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/altrom.inc                                                                      ;         ;
; altram.inc                                                               ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/altram.inc                                                                      ;         ;
; altdpram.inc                                                             ; yes             ; Megafunction                 ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                                                    ;         ;
; db/altsyncram_nog1.tdf                                                   ; yes             ; Auto-Generated Megafunction  ; d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/db/altsyncram_nog1.tdf                                                   ;         ;
+--------------------------------------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------------------------------+---------+


+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                            ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Estimated Total logic elements              ; 992                      ;
;                                             ;                          ;
; Total combinational functions               ; 781                      ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 375                      ;
;     -- 3 input functions                    ; 190                      ;
;     -- <=2 input functions                  ; 216                      ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 669                      ;
;     -- arithmetic mode                      ; 112                      ;
;                                             ;                          ;
; Total registers                             ; 522                      ;
;     -- Dedicated logic registers            ; 522                      ;
;     -- I/O registers                        ; 0                        ;
;                                             ;                          ;
; I/O pins                                    ; 21                       ;
; Total memory bits                           ; 512                      ;
; Embedded Multiplier 9-bit elements          ; 0                        ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO ;
; Maximum fan-out                             ; 318                      ;
; Total fan-out                               ; 4408                     ;
; Average fan-out                             ; 3.24                     ;
+---------------------------------------------+--------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                       ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                        ; Library Name ;
+--------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |top                                                                                             ; 781 (1)           ; 522 (0)      ; 512         ; 0            ; 0       ; 0         ; 21   ; 0            ; |top                                                                                                                                                                                                                                                                                       ; work         ;
;    |JTAG_MM:U_jtag_mm|                                                                           ; 668 (0)           ; 444 (0)      ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm                                                                                                                                                                                                                                                                     ; JTAG_MM      ;
;       |JTAG_MM_PIN:pin|                                                                          ; 8 (8)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin                                                                                                                                                                                                                                                     ; JTAG_MM      ;
;       |JTAG_MM_POUT:pout|                                                                        ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout                                                                                                                                                                                                                                                   ; JTAG_MM      ;
;       |JTAG_MM_master_0:master_0|                                                                ; 602 (0)           ; 386 (0)      ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0                                                                                                                                                                                                                                           ; JTAG_MM      ;
;          |altera_avalon_packets_to_master:transacto|                                             ; 188 (0)           ; 69 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto                                                                                                                                                                                                 ; JTAG_MM      ;
;             |packets_to_master:p2m|                                                              ; 188 (188)         ; 69 (69)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m                                                                                                                                                                           ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:fifo|                                                            ; 31 (31)           ; 24 (24)      ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo                                                                                                                                                                                                                ; JTAG_MM      ;
;             |altsyncram:mem_rtl_0|                                                               ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0                                                                                                                                                                                           ; work         ;
;                |altsyncram_nog1:auto_generated|                                                  ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated                                                                                                                                                            ; work         ;
;          |altera_avalon_st_bytes_to_packets:b2p|                                                 ; 15 (15)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p                                                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|                      ; 338 (0)           ; 263 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master                                                                                                                                                                          ; JTAG_MM      ;
;             |altera_jtag_dc_streaming:normal.jtag_dc_streaming|                                  ; 338 (0)           ; 263 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming                                                                                                                        ; JTAG_MM      ;
;                |altera_avalon_st_clock_crosser:sink_crosser|                                     ; 16 (4)            ; 47 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser                                                                            ; JTAG_MM      ;
;                   |altera_avalon_st_pipeline_base:output_stage|                                  ; 12 (12)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage                                ; JTAG_MM      ;
;                   |altera_std_synchronizer:in_to_out_synchronizer|                               ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer                             ; work         ;
;                   |altera_std_synchronizer:out_to_in_synchronizer|                               ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer                             ; work         ;
;                |altera_jtag_src_crosser:source_crosser|                                          ; 1 (0)             ; 27 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser                                                                                 ; JTAG_MM      ;
;                   |altera_jtag_control_signal_crosser:crosser|                                   ; 1 (1)             ; 9 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser                                      ; JTAG_MM      ;
;                      |altera_std_synchronizer:synchronizer|                                      ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ; work         ;
;                |altera_jtag_streaming:jtag_streaming|                                            ; 321 (304)         ; 186 (167)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming                                                                                   ; JTAG_MM      ;
;                   |altera_avalon_st_idle_inserter:idle_inserter|                                 ; 6 (6)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter                                      ; JTAG_MM      ;
;                   |altera_avalon_st_idle_remover:idle_remover|                                   ; 8 (8)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover                                        ; JTAG_MM      ;
;                   |altera_jtag_sld_node:node|                                                    ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node                                                         ; JTAG_MM      ;
;                      |sld_virtual_jtag_basic:sld_virtual_jtag_component|                         ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component       ; work         ;
;                   |altera_std_synchronizer:clock_sense_reset_n_synchronizer|                     ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer                          ; work         ;
;                   |altera_std_synchronizer:clock_sensor_synchronizer|                            ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer                                 ; work         ;
;                   |altera_std_synchronizer:clock_to_sample_div2_synchronizer|                    ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer                         ; work         ;
;                   |altera_std_synchronizer:reset_to_sample_synchronizer|                         ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer                              ; work         ;
;                |altera_std_synchronizer:synchronizer|                                            ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer                                                                                   ; work         ;
;          |altera_avalon_st_packets_to_bytes:p2b|                                                 ; 30 (30)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b                                                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_reset_controller:rst_controller|                                                ; 0 (0)             ; 3 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller                                                                                                                                                                                                    ; JTAG_MM      ;
;             |altera_reset_synchronizer:alt_rst_sync_uq1|                                         ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                         ; JTAG_MM      ;
;       |JTAG_MM_mm_interconnect_0:mm_interconnect_0|                                              ; 48 (0)            ; 39 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0                                                                                                                                                                                                                         ; JTAG_MM      ;
;          |JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux|                               ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux                                                                                                                                                                 ; JTAG_MM      ;
;          |JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|                                   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux                                                                                                                                                                     ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|       ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo                                                                                                                                         ; JTAG_MM      ;
;          |altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|      ; 5 (5)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo                                                                                                                                        ; JTAG_MM      ;
;          |altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent| ; 3 (3)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent                                                                                                                                   ; JTAG_MM      ;
;          |altera_merlin_slave_translator:pin_s1_translator|                                      ; 6 (6)             ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator                                                                                                                                                                        ; JTAG_MM      ;
;          |altera_merlin_slave_translator:pout_s1_translator|                                     ; 8 (8)             ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator                                                                                                                                                                       ; JTAG_MM      ;
;          |altera_merlin_traffic_limiter:limiter|                                                 ; 8 (8)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter                                                                                                                                                                                   ; JTAG_MM      ;
;       |altera_reset_controller:rst_controller|                                                   ; 0 (0)             ; 3 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller                                                                                                                                                                                                                              ; JTAG_MM      ;
;          |altera_reset_synchronizer:alt_rst_sync_uq1|                                            ; 0 (0)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1                                                                                                                                                                                   ; JTAG_MM      ;
;    |sld_hub:auto_hub|                                                                            ; 112 (1)           ; 78 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|sld_hub:auto_hub                                                                                                                                                                                                                                                                      ; work         ;
;       |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|                                             ; 111 (74)          ; 78 (50)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst                                                                                                                                                                                                                         ; work         ;
;          |sld_rom_sr:hub_info_reg|                                                               ; 20 (20)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg                                                                                                                                                                                                 ; work         ;
;          |sld_shadow_jsm:shadow_jsm|                                                             ; 17 (17)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |top|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm                                                                                                                                                                                               ; work         ;
+--------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                                                  ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512  ; None ;
+---------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                 ;
+--------+------------------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+
; Vendor ; IP Core Name                       ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                          ; IP Include File                      ;
+--------+------------------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+
; Altera ; Qsys                               ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm                                                                                                                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_jtag_avalon_master          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0                                                                                                         ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_st_bytes_to_packets  ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p                                                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; channel_adapter                    ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_b2p_adapter:b2p_adapter                                                                ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_sc_fifo              ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo                                                                              ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_jtag_dc_streaming           ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master                                        ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_st_packets_to_bytes  ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b                                                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; channel_adapter                    ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_p2b_adapter:p2b_adapter                                                                ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_reset_controller            ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller                                                                  ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; timing_adapter                     ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_timing_adt:timing_adt                                                                  ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_packets_to_master    ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto                                                               ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_interconnect_wrapper ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0                                                                                       ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_router               ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router                                     ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_demultiplexer        ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux                               ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_multiplexer          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_multiplexer          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux_001                               ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_router               ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router                                         ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_router               ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router_001                                     ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_traffic_limiter      ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter                                                 ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_master_translator    ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator                            ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_master_agent         ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_slave_translator     ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator                                      ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_slave_agent          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent            ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_sc_fifo              ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo       ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_slave_translator     ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator                                     ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_slave_agent          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent           ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_sc_fifo              ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo      ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_demultiplexer        ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux                               ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_demultiplexer        ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux_001                           ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_merlin_multiplexer          ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_pio                  ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin                                                                                                                   ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_avalon_pio                  ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout                                                                                                                 ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
; Altera ; altera_reset_controller            ; 13.1    ; N/A          ; N/A          ; |top|JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller                                                                                            ; JTAG_MM/synthesis/../../JTAG_MM.qsys ;
+--------+------------------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state                                                                                                                                                                                                           ;
+-----------------------+----------------------+-----------------------+----------------------+---------------------+-------------------+---------------------+------------------+----------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------+
; Name                  ; state.READ_SEND_WAIT ; state.READ_SEND_ISSUE ; state.READ_DATA_WAIT ; state.READ_CMD_WAIT ; state.READ_ASSERT ; state.RETURN_PACKET ; state.WRITE_WAIT ; state.GET_WRITE_DATA ; state.GET_ADDR4 ; state.GET_ADDR3 ; state.GET_ADDR2 ; state.GET_ADDR1 ; state.GET_SIZE2 ; state.GET_SIZE1 ; state.GET_EXTRA ; state.0000 ;
+-----------------------+----------------------+-----------------------+----------------------+---------------------+-------------------+---------------------+------------------+----------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------+
; state.0000            ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0          ;
; state.GET_EXTRA       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 1          ;
; state.GET_SIZE1       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 1          ;
; state.GET_SIZE2       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 1          ;
; state.GET_ADDR1       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 1          ;
; state.GET_ADDR2       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.GET_ADDR3       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.GET_ADDR4       ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 1               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.GET_WRITE_DATA  ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 1                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.WRITE_WAIT      ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 1                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.RETURN_PACKET   ; 0                    ; 0                     ; 0                    ; 0                   ; 0                 ; 1                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.READ_ASSERT     ; 0                    ; 0                     ; 0                    ; 0                   ; 1                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.READ_CMD_WAIT   ; 0                    ; 0                     ; 0                    ; 1                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.READ_DATA_WAIT  ; 0                    ; 0                     ; 1                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.READ_SEND_ISSUE ; 0                    ; 1                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
; state.READ_SEND_WAIT  ; 1                    ; 0                     ; 0                    ; 0                   ; 0                 ; 0                   ; 0                ; 0                    ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 0               ; 1          ;
+-----------------------+----------------------+-----------------------+----------------------+---------------------+-------------------+---------------------+------------------+----------------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+-----------------+------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state ;
+-------------------------+----------------------+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                    ; read_state.ST_HEADER ; read_state.ST_READ_DATA ; read_state.ST_PADDED                                                                                                                                     ;
+-------------------------+----------------------+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; read_state.ST_HEADER    ; 0                    ; 0                       ; 0                                                                                                                                                        ;
; read_state.ST_PADDED    ; 1                    ; 0                       ; 1                                                                                                                                                        ;
; read_state.ST_READ_DATA ; 1                    ; 1                       ; 0                                                                                                                                                        ;
+-------------------------+----------------------+-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state ;
+---------------------------+---------------------------+-------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------+
; Name                      ; write_state.ST_WRITE_DATA ; write_state.ST_HEADER_2 ; write_state.ST_HEADER_1 ; write_state.ST_BYPASS                                                                                                    ;
+---------------------------+---------------------------+-------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------+
; write_state.ST_BYPASS     ; 0                         ; 0                       ; 0                       ; 0                                                                                                                        ;
; write_state.ST_HEADER_1   ; 0                         ; 0                       ; 1                       ; 1                                                                                                                        ;
; write_state.ST_HEADER_2   ; 0                         ; 1                       ; 0                       ; 1                                                                                                                        ;
; write_state.ST_WRITE_DATA ; 1                         ; 0                       ; 0                       ; 1                                                                                                                        ;
+---------------------------+---------------------------+-------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                                                                                                 ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|dreg[1]                              ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                                                    ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[6]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|dreg[0]                              ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer|dreg[1]                         ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|dreg[1]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[1]                                                                                   ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                                                                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                                                    ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[5]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer|din_s1                               ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer|dreg[0]                         ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|dreg[1]                                 ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|dreg[0]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|dreg[0]                                                                                   ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[0]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                                                                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[7]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[6]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[5]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[4]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[3]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[2]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|src_data[1]                                                                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[4]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer|din_s1                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|dreg[0]                                 ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer|din_s1                              ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer|din_s1                                                                                    ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[6] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[3]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer|din_s1                                  ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[5] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[2]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[4] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[1]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[6]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[3] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|dreg[0]                             ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[5]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[2] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer|din_s1                              ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[4]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[1] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[3]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|dreg[0] ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[2]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer|din_s1  ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[1]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|dreg[0]                          ; yes                                                              ; yes                                        ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer|din_s1                           ; yes                                                              ; yes                                        ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                              ; Reason for Removal                                                                                                                                                                                                                   ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][87]                                                                   ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][87]                                                                  ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[8..31]                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_chipselect_pre                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[8..31]                                                                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[8]                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_mgmt[0]             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[8..31]                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[0..23]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][87]                                                                   ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][87]                                                                  ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p|received_varchannel                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[1]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[2]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[2]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[3]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[3]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[4]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[4]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[5]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[5]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[6]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[6]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[7]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[7]                                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[0]                                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|last_channel[0]                                                                                                        ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter|last_dest_id[0]                                                                                                      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][103]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                 ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][74]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                 ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][103]                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][74]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|waitrequest_reset_override                                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|hold_waitrequest                                                     ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|waitrequest_reset_override                                                                                 ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|hold_waitrequest                                                     ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][103]                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][74]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][75]                                                                  ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][103]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][74]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                 ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][75]                                                                   ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                 ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3]    ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2]  ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1]    ; Merged with JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]  ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|channel_needs_esc                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[10]            ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                   ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy               ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2]  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68]                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy              ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|channel_escaped                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[9]             ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102]                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102]                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102]                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102]                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                                                               ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~20                                                                                                       ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~21                                                                                                       ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~22                                                                                                       ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state~23                                                                                                       ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~6          ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state~7          ; Lost fanout                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5..31]                                                                                                 ; Lost fanout                                                                                                                                                                                                                          ;
; Total Number of Removed Registers = 181                                                                                                                                                                                    ;                                                                                                                                                                                                                                      ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                   ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[31]                                                                                         ; Lost Fanouts              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[30],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[29],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[28],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[27],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[26],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[25],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[24],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[23],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[22],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[21],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[20],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[19],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[18],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[17],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[16],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[15],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[14],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[13],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[12],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[11],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[10],                                                                                                 ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[9],                                                                                                  ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[8],                                                                                                  ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[7],                                                                                                  ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[6],                                                                                                  ;
;                                                                                                                                                                                                                 ;                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[5]                                                                                                   ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                        ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68],                                                                ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0]  ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][75]                                                       ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68],                                                               ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[30]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[22]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[29]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[21]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[28]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[20]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[27]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[19]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[26]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[18]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[25]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[17]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[24]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[16]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[23]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[15]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[22]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[14]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[21]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[13]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[20]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[12]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[19]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[11]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[18]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[10]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[17]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[9]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[16]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[8]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[15]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[7]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[14]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[6]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[13]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[5]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[12]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[4]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[11]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[3]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[10]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[2]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[9]                                                                              ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[1]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[8]                                                                              ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[0]                                                                                          ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[31]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[31]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[30]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[30]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[29]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[29]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[28]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[28]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[27]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[27]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[26]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[26]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[25]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[25]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[24]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[24]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[23]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[23]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[22]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[22]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[21]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[21]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[20]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[20]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[19]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[19]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[18]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[18]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[17]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[17]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[16]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[16]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][87]                                                        ; Lost Fanouts              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][87]                                                                 ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[14]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[14]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[13]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[13]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[12]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[12]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[11]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[11]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[10]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[10]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[9]                                                                                                                                                                   ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[9]                                                                                        ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[15]                                                                                                                                                                  ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[15]                                                                                       ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[8]                                                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|channel_escaped                                                                                                                        ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][87]                                                       ; Lost Fanouts              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][87]                                                                ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|av_readdata_pre[31]                                                                             ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|read_data_buffer[23]                                                                                         ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[10] ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_info[9]           ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102]                                                      ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102]                                                               ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102]                                                       ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102]                                                                ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
; JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin|readdata[8]                                                                                                                                                                   ; Stuck at GND              ; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|av_readdata_pre[8]                                                                                        ;
;                                                                                                                                                                                                                 ; due to stuck port data_in ;                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 522   ;
; Number of registers using Synchronous Clear  ; 13    ;
; Number of registers using Synchronous Load   ; 56    ;
; Number of registers using Asynchronous Clear ; 289   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 348   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                                                      ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                                                       ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                                             ; 55      ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out                                                   ; 159     ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                                              ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent|hold_waitrequest                                                    ; 4       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|stored_channel[0]                                                                                                                     ; 3       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0]                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                                              ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]                                                    ; 1       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|empty                                                                                                                                            ; 2       ;
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|clock_sense_reset_n ; 8       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                       ; 1       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                            ; 2       ;
; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                            ; 3       ;
; Total number of inverted registers = 13                                                                                                                                                                                 ;         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                                                                                                                                ;
+---------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------+
; Register Name                                                                                     ; Megafunction                                                                     ; Type ;
+---------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------+
; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|internal_out_payload[0..7] ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rtl_0 ; RAM  ;
+---------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 18 bits   ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_control[1]                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_debug[0]                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator|wait_latency_counter[1]                                                                                                      ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator|wait_latency_counter[0]                                                                                                       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_out_bit_counter[0]                ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_data_bit_counter[2]                 ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|bypass_bit_counter[4]                    ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_data_bit_counter[1]                ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|header_in_bit_counter[1]                 ;
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[0]  ;
; 4:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|valid_write_data_length_byte_counter[17] ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[8]                                                                                                                       ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|counter[4]                                                                                                                       ;
; 7:1                ; 7 bits    ; 28 LEs        ; 28 LEs               ; 0 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b|out_data[7]                                                                                                                                                ;
; 5:1                ; 9 bits    ; 27 LEs        ; 9 LEs                ; 18 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[3]              ;
; 5:1                ; 10 bits   ; 30 LEs        ; 10 LEs               ; 20 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|scan_length_byte_counter[13]             ;
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[31]                                                                                                                      ;
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[18]                                                                                                                      ;
; 8:1                ; 8 bits    ; 40 LEs        ; 8 LEs                ; 32 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[11]                                                                                                                      ;
; 8:1                ; 6 bits    ; 30 LEs        ; 6 LEs                ; 24 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|address[2]                                                                                                                       ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[2]                    ;
; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|padded_bit_counter[5]                    ;
; 12:1               ; 2 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|current_byte[0]                                                                                                                  ;
; 13:1               ; 5 bits    ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|dr_data_out[3]                           ;
; 16:1               ; 7 bits    ; 70 LEs        ; 21 LEs               ; 49 LEs                 ; Yes        ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|out_data[6]                                                                                                                      ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decoded_read_data_length[11]             ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decoded_read_data_length[10]             ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decoded_write_data_length[14]            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|decoded_write_data_length[7]             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state                               ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state                              ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state                              ;
; 15:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state                                                                                                                            ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |top|JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state                                                                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                       ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                       ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                      ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ;
+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                                                                                          ;
+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; clock_sense_reset_n                                                                                                                                                                         ;
+---------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                         ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                         ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                        ;
+-----------------------------+------------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                           ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                           ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                           ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                           ;
+-----------------------------+------------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                     ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                 ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                 ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                 ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                                ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                                ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                                ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ;
+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                    ;
+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[6]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[5]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[4]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[3]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[2]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                               ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                               ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                               ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                               ;
+-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[6]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[5]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[4]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[3]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[2]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                            ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                                                                                        ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; src_data[7]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[6]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[5]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[4]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[3]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[2]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[1]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[0]                                                                                                                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[0]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[7]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[6]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[5]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[4]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[3]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[2]~reg0                                                                                                                                                                          ;
; PRESERVE_REGISTER ; ON    ; -    ; src_data[1]~reg0                                                                                                                                                                          ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                                                                                             ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                                                                                                         ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                         ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                                                                                                         ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[6]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[6]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[5]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[5]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[4]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[4]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[3]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[3]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[2]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[2]                                                                                                                                                                                                                                        ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[1]                                                                                                                                                                                                                                        ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                                                        ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[1]                                                                                                                                                                                                                                        ;
+-----------------------------+------------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                            ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                            ;
+-------------------+-------+------+-------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                                                    ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                                                ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                                                ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                          ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                         ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                       ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                          ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                         ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                       ;
+-----------------+-------+------+-------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux_001 ;
+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                                                              ;
+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------+
; MESSAGE_DISABLE ; 15610 ; -    ; clk                                                                                                             ;
; MESSAGE_DISABLE ; 15610 ; -    ; reset                                                                                                           ;
+-----------------+-------+------+-----------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                      ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                  ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                  ;
+-------------------+-------+------+-----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                          ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[0]                                                      ;
; PRESERVE_REGISTER ; on    ; -    ; altera_reset_synchronizer_int_chain[1]                                                      ;
+-------------------+-------+------+---------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0|altsyncram_nog1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                  ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                   ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0 ;
+----------------+-------+-----------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                            ;
+----------------+-------+-----------------------------------------------------------------+
; USE_PLI        ; 0     ; Signed Integer                                                  ;
; PLI_PORT       ; 50000 ; Signed Integer                                                  ;
; FIFO_DEPTHS    ; 2     ; Signed Integer                                                  ;
+----------------+-------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master ;
+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+
; Parameter Name       ; Value ; Type                                                                                                                       ;
+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+
; PURPOSE              ; 1     ; Signed Integer                                                                                                             ;
; UPSTREAM_FIFO_SIZE   ; 0     ; Signed Integer                                                                                                             ;
; DOWNSTREAM_FIFO_SIZE ; 64    ; Signed Integer                                                                                                             ;
; MGMT_CHANNEL_WIDTH   ; -1    ; Signed Integer                                                                                                             ;
; USE_PLI              ; 0     ; Signed Integer                                                                                                             ;
; PLI_PORT             ; 50000 ; Signed Integer                                                                                                             ;
+----------------------+-------+----------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming ;
+--------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name           ; Value ; Type                                                                                                                                                                     ;
+--------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PURPOSE                  ; 1     ; Signed Integer                                                                                                                                                           ;
; UPSTREAM_FIFO_SIZE       ; 0     ; Signed Integer                                                                                                                                                           ;
; DOWNSTREAM_FIFO_SIZE     ; 64    ; Signed Integer                                                                                                                                                           ;
; MGMT_CHANNEL_WIDTH       ; -1    ; Signed Integer                                                                                                                                                           ;
; TCK_TO_SYSCLK_SYNC_DEPTH ; 8     ; Signed Integer                                                                                                                                                           ;
; SYSCLK_TO_TCK_SYNC_DEPTH ; 3     ; Signed Integer                                                                                                                                                           ;
+--------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 3     ; Signed Integer                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming ;
+--------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name           ; Value ; Type                                                                                                                                                                                                          ;
+--------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PURPOSE                  ; 1     ; Signed Integer                                                                                                                                                                                                ;
; UPSTREAM_FIFO_SIZE       ; 0     ; Signed Integer                                                                                                                                                                                                ;
; DOWNSTREAM_FIFO_SIZE     ; 64    ; Signed Integer                                                                                                                                                                                                ;
; MGMT_CHANNEL_WIDTH       ; -1    ; Signed Integer                                                                                                                                                                                                ;
; TCK_TO_SYSCLK_SYNC_DEPTH ; 8     ; Signed Integer                                                                                                                                                                                                ;
; SYSCLK_TO_TCK_SYNC_DEPTH ; 3     ; Signed Integer                                                                                                                                                                                                ;
+--------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 3     ; Signed Integer                                                                                                                                                                                                                                                            ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                         ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 3     ; Signed Integer                                                                                                                                                                                                                                                               ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 3     ; Signed Integer                                                                                                                                                                                                                                                                    ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                             ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 8     ; Signed Integer                                                                                                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; TCK_FREQ_MHZ   ; 20    ; Signed Integer                                                                                                                                                                                                                                    ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value                  ; Type                                                                                                                                                                                                                                                                      ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sld_mfg_id              ; 110                    ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_type_id             ; 132                    ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_version             ; 1                      ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_instance_index      ; 0                      ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_auto_instance_index ; YES                    ; String                                                                                                                                                                                                                                                                    ;
; sld_ir_width            ; 3                      ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_sim_n_scan          ; 0                      ; Signed Integer                                                                                                                                                                                                                                                            ;
; sld_sim_action          ;                        ; String                                                                                                                                                                                                                                                                    ;
; sld_sim_total_length    ; 0                      ; Signed Integer                                                                                                                                                                                                                                                            ;
; lpm_type                ; sld_virtual_jtag_basic ; String                                                                                                                                                                                                                                                                    ;
; lpm_hint                ; UNUSED                 ; String                                                                                                                                                                                                                                                                    ;
+-------------------------+------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                                                                      ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                                                                            ;
; BITS_PER_SYMBOL     ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; FORWARD_SYNC_DEPTH  ; 3     ; Signed Integer                                                                                                                                                                                                            ;
; BACKWARD_SYNC_DEPTH ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; USE_OUTPUT_PIPELINE ; 1     ; Signed Integer                                                                                                                                                                                                            ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:in_to_out_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 3     ; Signed Integer                                                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_std_synchronizer:out_to_in_synchronizer ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 8     ; Signed Integer                                                                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage ;
+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value ; Type                                                                                                                                                                                                                                                                     ;
+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT ; 1     ; Signed Integer                                                                                                                                                                                                                                                           ;
; BITS_PER_SYMBOL  ; 8     ; Signed Integer                                                                                                                                                                                                                                                           ;
; PIPELINE_READY   ; 1     ; Signed Integer                                                                                                                                                                                                                                                           ;
+------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                      ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 8     ; Signed Integer                                                                                                                                                                                                            ;
; SYNC_DEPTH     ; 8     ; Signed Integer                                                                                                                                                                                                            ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                 ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYNC_DEPTH     ; 8     ; Signed Integer                                                                                                                                                                                                                                                       ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser|altera_std_synchronizer:synchronizer ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                                                                                      ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 8     ; Signed Integer                                                                                                                                                                                                                                                                                            ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                  ;
+---------------------+-------+---------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                        ;
; BITS_PER_SYMBOL     ; 8     ; Signed Integer                                                                        ;
; FIFO_DEPTH          ; 64    ; Signed Integer                                                                        ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                        ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                        ;
; USE_PACKETS         ; 0     ; Signed Integer                                                                        ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                        ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                        ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                        ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                        ;
; EMPTY_LATENCY       ; 3     ; Signed Integer                                                                        ;
; USE_MEMORY_BLOCKS   ; 1     ; Signed Integer                                                                        ;
; DATA_WIDTH          ; 8     ; Signed Integer                                                                        ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                        ;
+---------------------+-------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; CHANNEL_WIDTH  ; 8     ; Signed Integer                                                                                        ;
; ENCODING       ; 0     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
; CHANNEL_WIDTH  ; 8     ; Signed Integer                                                                                        ;
; ENCODING       ; 0     ; Signed Integer                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto ;
+-----------------------+-------+----------------------------------------------------------------------------------------------------+
; Parameter Name        ; Value ; Type                                                                                               ;
+-----------------------+-------+----------------------------------------------------------------------------------------------------+
; EXPORT_MASTER_SIGNALS ; 0     ; Signed Integer                                                                                     ;
; FIFO_DEPTHS           ; 2     ; Signed Integer                                                                                     ;
; FIFO_WIDTHU           ; 1     ; Signed Integer                                                                                     ;
; FAST_VER              ; 0     ; Signed Integer                                                                                     ;
+-----------------------+-------+----------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m ;
+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------+
; Parameter Name        ; Value ; Type                                                                                                                     ;
+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------+
; EXPORT_MASTER_SIGNALS ; 0     ; Signed Integer                                                                                                           ;
+-----------------------+-------+--------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller ;
+---------------------------+----------+------------------------------------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                                                     ;
+---------------------------+----------+------------------------------------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 1        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                                           ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                                           ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                                                   ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                                           ;
; RESET_REQUEST_PRESENT     ; 0        ; Signed Integer                                                                           ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                                           ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                                           ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                                           ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                                           ;
+---------------------------+----------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                              ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                                                   ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                    ;
+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                  ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                                                        ;
; DEPTH          ; 2     ; Signed Integer                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name              ; Value ; Type                                                                                                                            ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                ; 32    ; Signed Integer                                                                                                                  ;
; AV_DATA_W                   ; 32    ; Signed Integer                                                                                                                  ;
; AV_BURSTCOUNT_W             ; 1     ; Signed Integer                                                                                                                  ;
; AV_BYTEENABLE_W             ; 4     ; Signed Integer                                                                                                                  ;
; USE_BURSTCOUNT              ; 0     ; Signed Integer                                                                                                                  ;
; USE_BEGINBURSTTRANSFER      ; 0     ; Signed Integer                                                                                                                  ;
; USE_BEGINTRANSFER           ; 0     ; Signed Integer                                                                                                                  ;
; USE_CHIPSELECT              ; 0     ; Signed Integer                                                                                                                  ;
; USE_READ                    ; 1     ; Signed Integer                                                                                                                  ;
; USE_READDATAVALID           ; 1     ; Signed Integer                                                                                                                  ;
; USE_WRITE                   ; 1     ; Signed Integer                                                                                                                  ;
; USE_WAITREQUEST             ; 1     ; Signed Integer                                                                                                                  ;
; USE_WRITERESPONSE           ; 0     ; Signed Integer                                                                                                                  ;
; USE_READRESPONSE            ; 0     ; Signed Integer                                                                                                                  ;
; AV_REGISTERINCOMINGSIGNALS  ; 0     ; Signed Integer                                                                                                                  ;
; AV_SYMBOLS_PER_WORD         ; 4     ; Signed Integer                                                                                                                  ;
; AV_ADDRESS_SYMBOLS          ; 1     ; Signed Integer                                                                                                                  ;
; AV_CONSTANT_BURST_BEHAVIOR  ; 0     ; Signed Integer                                                                                                                  ;
; AV_BURSTCOUNT_SYMBOLS       ; 0     ; Signed Integer                                                                                                                  ;
; AV_LINEWRAPBURSTS           ; 0     ; Signed Integer                                                                                                                  ;
; UAV_ADDRESS_W               ; 32    ; Signed Integer                                                                                                                  ;
; UAV_BURSTCOUNT_W            ; 3     ; Signed Integer                                                                                                                  ;
; UAV_CONSTANT_BURST_BEHAVIOR ; 0     ; Signed Integer                                                                                                                  ;
+-----------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                                ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                      ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                      ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                      ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                      ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                      ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                      ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                      ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                      ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                      ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                      ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                      ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                      ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                      ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                      ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                      ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                      ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                      ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                      ;
; UAV_ADDRESS_W                  ; 32    ; Signed Integer                                                                                                      ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                      ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                      ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                      ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                      ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                      ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                      ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                      ;
+--------------------------------+-------+---------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------+
; Parameter Name                 ; Value ; Type                                                                                                               ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------+
; AV_ADDRESS_W                   ; 2     ; Signed Integer                                                                                                     ;
; AV_DATA_W                      ; 32    ; Signed Integer                                                                                                     ;
; AV_BURSTCOUNT_W                ; 1     ; Signed Integer                                                                                                     ;
; AV_BYTEENABLE_W                ; 1     ; Signed Integer                                                                                                     ;
; UAV_BYTEENABLE_W               ; 4     ; Signed Integer                                                                                                     ;
; AV_READLATENCY                 ; 0     ; Signed Integer                                                                                                     ;
; AV_READ_WAIT_CYCLES            ; 1     ; Signed Integer                                                                                                     ;
; AV_WRITE_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                     ;
; AV_SETUP_WAIT_CYCLES           ; 0     ; Signed Integer                                                                                                     ;
; AV_DATA_HOLD_CYCLES            ; 0     ; Signed Integer                                                                                                     ;
; USE_READDATAVALID              ; 0     ; Signed Integer                                                                                                     ;
; USE_WAITREQUEST                ; 0     ; Signed Integer                                                                                                     ;
; USE_READRESPONSE               ; 0     ; Signed Integer                                                                                                     ;
; USE_WRITERESPONSE              ; 0     ; Signed Integer                                                                                                     ;
; AV_SYMBOLS_PER_WORD            ; 4     ; Signed Integer                                                                                                     ;
; AV_ADDRESS_SYMBOLS             ; 0     ; Signed Integer                                                                                                     ;
; AV_BURSTCOUNT_SYMBOLS          ; 0     ; Signed Integer                                                                                                     ;
; BITS_PER_WORD                  ; 2     ; Signed Integer                                                                                                     ;
; UAV_ADDRESS_W                  ; 32    ; Signed Integer                                                                                                     ;
; UAV_BURSTCOUNT_W               ; 3     ; Signed Integer                                                                                                     ;
; UAV_DATA_W                     ; 32    ; Signed Integer                                                                                                     ;
; AV_CONSTANT_BURST_BEHAVIOR     ; 0     ; Signed Integer                                                                                                     ;
; UAV_CONSTANT_BURST_BEHAVIOR    ; 0     ; Signed Integer                                                                                                     ;
; CHIPSELECT_THROUGH_READLATENCY ; 0     ; Signed Integer                                                                                                     ;
; USE_UAV_CLKEN                  ; 0     ; Signed Integer                                                                                                     ;
; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0     ; Signed Integer                                                                                                     ;
+--------------------------------+-------+--------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                                         ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_QOS_H                 ; 86    ; Signed Integer                                                                                                                                               ;
; PKT_QOS_L                 ; 86    ; Signed Integer                                                                                                                                               ;
; PKT_DATA_SIDEBAND_H       ; 84    ; Signed Integer                                                                                                                                               ;
; PKT_DATA_SIDEBAND_L       ; 84    ; Signed Integer                                                                                                                                               ;
; PKT_ADDR_SIDEBAND_H       ; 83    ; Signed Integer                                                                                                                                               ;
; PKT_ADDR_SIDEBAND_L       ; 83    ; Signed Integer                                                                                                                                               ;
; PKT_CACHE_H               ; 96    ; Signed Integer                                                                                                                                               ;
; PKT_CACHE_L               ; 93    ; Signed Integer                                                                                                                                               ;
; PKT_THREAD_ID_H           ; 89    ; Signed Integer                                                                                                                                               ;
; PKT_THREAD_ID_L           ; 89    ; Signed Integer                                                                                                                                               ;
; PKT_BEGIN_BURST           ; 85    ; Signed Integer                                                                                                                                               ;
; PKT_PROTECTION_H          ; 92    ; Signed Integer                                                                                                                                               ;
; PKT_PROTECTION_L          ; 90    ; Signed Integer                                                                                                                                               ;
; PKT_BURSTWRAP_H           ; 77    ; Signed Integer                                                                                                                                               ;
; PKT_BURSTWRAP_L           ; 77    ; Signed Integer                                                                                                                                               ;
; PKT_BYTE_CNT_H            ; 76    ; Signed Integer                                                                                                                                               ;
; PKT_BYTE_CNT_L            ; 74    ; Signed Integer                                                                                                                                               ;
; PKT_ADDR_H                ; 67    ; Signed Integer                                                                                                                                               ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                               ;
; PKT_BURST_SIZE_H          ; 80    ; Signed Integer                                                                                                                                               ;
; PKT_BURST_SIZE_L          ; 78    ; Signed Integer                                                                                                                                               ;
; PKT_BURST_TYPE_H          ; 82    ; Signed Integer                                                                                                                                               ;
; PKT_BURST_TYPE_L          ; 81    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_EXCLUSIVE       ; 73    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_LOCK            ; 72    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_COMPRESSED_READ ; 68    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_POSTED          ; 69    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_WRITE           ; 70    ; Signed Integer                                                                                                                                               ;
; PKT_TRANS_READ            ; 71    ; Signed Integer                                                                                                                                               ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                               ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                               ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                               ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                               ;
; PKT_SRC_ID_H              ; 87    ; Signed Integer                                                                                                                                               ;
; PKT_SRC_ID_L              ; 87    ; Signed Integer                                                                                                                                               ;
; PKT_DEST_ID_H             ; 88    ; Signed Integer                                                                                                                                               ;
; PKT_DEST_ID_L             ; 88    ; Signed Integer                                                                                                                                               ;
; PKT_RESPONSE_STATUS_L     ; 97    ; Signed Integer                                                                                                                                               ;
; PKT_RESPONSE_STATUS_H     ; 98    ; Signed Integer                                                                                                                                               ;
; PKT_ORI_BURST_SIZE_L      ; 99    ; Signed Integer                                                                                                                                               ;
; PKT_ORI_BURST_SIZE_H      ; 101   ; Signed Integer                                                                                                                                               ;
; ST_DATA_W                 ; 102   ; Signed Integer                                                                                                                                               ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                               ;
; AV_BURSTCOUNT_W           ; 3     ; Signed Integer                                                                                                                                               ;
; ID                        ; 0     ; Signed Integer                                                                                                                                               ;
; SUPPRESS_0_BYTEEN_RSP     ; 0     ; Signed Integer                                                                                                                                               ;
; BURSTWRAP_VALUE           ; 1     ; Signed Integer                                                                                                                                               ;
; CACHE_VALUE               ; 0     ; Signed Integer                                                                                                                                               ;
; SECURE_ACCESS_BIT         ; 1     ; Signed Integer                                                                                                                                               ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                               ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                               ;
; PKT_BURSTWRAP_W           ; 1     ; Signed Integer                                                                                                                                               ;
; PKT_BYTE_CNT_W            ; 3     ; Signed Integer                                                                                                                                               ;
; PKT_PROTECTION_W          ; 3     ; Signed Integer                                                                                                                                               ;
; PKT_ADDR_W                ; 32    ; Signed Integer                                                                                                                                               ;
; PKT_DATA_W                ; 32    ; Signed Integer                                                                                                                                               ;
; PKT_BYTEEN_W              ; 4     ; Signed Integer                                                                                                                                               ;
; PKT_SRC_ID_W              ; 1     ; Signed Integer                                                                                                                                               ;
; PKT_DEST_ID_W             ; 1     ; Signed Integer                                                                                                                                               ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                               ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 85    ; Signed Integer                                                                                                                                     ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                     ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                     ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                     ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                     ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                     ;
; PKT_ADDR_H                ; 67    ; Signed Integer                                                                                                                                     ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                     ;
; PKT_TRANS_LOCK            ; 72    ; Signed Integer                                                                                                                                     ;
; PKT_TRANS_COMPRESSED_READ ; 68    ; Signed Integer                                                                                                                                     ;
; PKT_TRANS_POSTED          ; 69    ; Signed Integer                                                                                                                                     ;
; PKT_TRANS_WRITE           ; 70    ; Signed Integer                                                                                                                                     ;
; PKT_TRANS_READ            ; 71    ; Signed Integer                                                                                                                                     ;
; PKT_SRC_ID_H              ; 87    ; Signed Integer                                                                                                                                     ;
; PKT_SRC_ID_L              ; 87    ; Signed Integer                                                                                                                                     ;
; PKT_DEST_ID_H             ; 88    ; Signed Integer                                                                                                                                     ;
; PKT_DEST_ID_L             ; 88    ; Signed Integer                                                                                                                                     ;
; PKT_BURSTWRAP_H           ; 77    ; Signed Integer                                                                                                                                     ;
; PKT_BURSTWRAP_L           ; 77    ; Signed Integer                                                                                                                                     ;
; PKT_BYTE_CNT_H            ; 76    ; Signed Integer                                                                                                                                     ;
; PKT_BYTE_CNT_L            ; 74    ; Signed Integer                                                                                                                                     ;
; PKT_PROTECTION_H          ; 92    ; Signed Integer                                                                                                                                     ;
; PKT_PROTECTION_L          ; 90    ; Signed Integer                                                                                                                                     ;
; PKT_RESPONSE_STATUS_H     ; 98    ; Signed Integer                                                                                                                                     ;
; PKT_RESPONSE_STATUS_L     ; 97    ; Signed Integer                                                                                                                                     ;
; PKT_BURST_SIZE_H          ; 80    ; Signed Integer                                                                                                                                     ;
; PKT_BURST_SIZE_L          ; 78    ; Signed Integer                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_L      ; 99    ; Signed Integer                                                                                                                                     ;
; PKT_ORI_BURST_SIZE_H      ; 101   ; Signed Integer                                                                                                                                     ;
; ST_DATA_W                 ; 102   ; Signed Integer                                                                                                                                     ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                     ;
; ADDR_W                    ; 32    ; Signed Integer                                                                                                                                     ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                     ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                     ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                     ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                     ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                     ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                     ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                     ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                     ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                     ;
; FIFO_DATA_W               ; 103   ; Signed Integer                                                                                                                                     ;
+---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                        ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 32    ; Signed Integer                                                                                                                                                                                              ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                              ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                              ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                              ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                              ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                          ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                                ;
; BITS_PER_SYMBOL     ; 103   ; Signed Integer                                                                                                                                                ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                                ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                                ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                                ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                                ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                                ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                                ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                                ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                                ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                                ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                                ;
; DATA_WIDTH          ; 103   ; Signed Integer                                                                                                                                                ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                                ;
+---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                                                              ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; PKT_BEGIN_BURST           ; 85    ; Signed Integer                                                                                                                                    ;
; PKT_DATA_H                ; 31    ; Signed Integer                                                                                                                                    ;
; PKT_DATA_L                ; 0     ; Signed Integer                                                                                                                                    ;
; PKT_SYMBOL_W              ; 8     ; Signed Integer                                                                                                                                    ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                                                                    ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                                                                    ;
; PKT_ADDR_H                ; 67    ; Signed Integer                                                                                                                                    ;
; PKT_ADDR_L                ; 36    ; Signed Integer                                                                                                                                    ;
; PKT_TRANS_LOCK            ; 72    ; Signed Integer                                                                                                                                    ;
; PKT_TRANS_COMPRESSED_READ ; 68    ; Signed Integer                                                                                                                                    ;
; PKT_TRANS_POSTED          ; 69    ; Signed Integer                                                                                                                                    ;
; PKT_TRANS_WRITE           ; 70    ; Signed Integer                                                                                                                                    ;
; PKT_TRANS_READ            ; 71    ; Signed Integer                                                                                                                                    ;
; PKT_SRC_ID_H              ; 87    ; Signed Integer                                                                                                                                    ;
; PKT_SRC_ID_L              ; 87    ; Signed Integer                                                                                                                                    ;
; PKT_DEST_ID_H             ; 88    ; Signed Integer                                                                                                                                    ;
; PKT_DEST_ID_L             ; 88    ; Signed Integer                                                                                                                                    ;
; PKT_BURSTWRAP_H           ; 77    ; Signed Integer                                                                                                                                    ;
; PKT_BURSTWRAP_L           ; 77    ; Signed Integer                                                                                                                                    ;
; PKT_BYTE_CNT_H            ; 76    ; Signed Integer                                                                                                                                    ;
; PKT_BYTE_CNT_L            ; 74    ; Signed Integer                                                                                                                                    ;
; PKT_PROTECTION_H          ; 92    ; Signed Integer                                                                                                                                    ;
; PKT_PROTECTION_L          ; 90    ; Signed Integer                                                                                                                                    ;
; PKT_RESPONSE_STATUS_H     ; 98    ; Signed Integer                                                                                                                                    ;
; PKT_RESPONSE_STATUS_L     ; 97    ; Signed Integer                                                                                                                                    ;
; PKT_BURST_SIZE_H          ; 80    ; Signed Integer                                                                                                                                    ;
; PKT_BURST_SIZE_L          ; 78    ; Signed Integer                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_L      ; 99    ; Signed Integer                                                                                                                                    ;
; PKT_ORI_BURST_SIZE_H      ; 101   ; Signed Integer                                                                                                                                    ;
; ST_DATA_W                 ; 102   ; Signed Integer                                                                                                                                    ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                                                                    ;
; ADDR_W                    ; 32    ; Signed Integer                                                                                                                                    ;
; AVS_DATA_W                ; 32    ; Signed Integer                                                                                                                                    ;
; AVS_BURSTCOUNT_W          ; 3     ; Signed Integer                                                                                                                                    ;
; PKT_SYMBOLS               ; 4     ; Signed Integer                                                                                                                                    ;
; PREVENT_FIFO_OVERFLOW     ; 1     ; Signed Integer                                                                                                                                    ;
; SUPPRESS_0_BYTEEN_CMD     ; 0     ; Signed Integer                                                                                                                                    ;
; USE_READRESPONSE          ; 0     ; Signed Integer                                                                                                                                    ;
; USE_WRITERESPONSE         ; 0     ; Signed Integer                                                                                                                                    ;
; AVS_BE_W                  ; 4     ; Signed Integer                                                                                                                                    ;
; BURST_SIZE_W              ; 3     ; Signed Integer                                                                                                                                    ;
; FIFO_DATA_W               ; 103   ; Signed Integer                                                                                                                                    ;
+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                       ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADDR_W         ; 32    ; Signed Integer                                                                                                                                                                                             ;
; BURSTWRAP_W    ; 1     ; Signed Integer                                                                                                                                                                                             ;
; BYTE_CNT_W     ; 3     ; Signed Integer                                                                                                                                                                                             ;
; PKT_SYMBOLS    ; 4     ; Signed Integer                                                                                                                                                                                             ;
; BURST_SIZE_W   ; 3     ; Signed Integer                                                                                                                                                                                             ;
+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                         ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SYMBOLS_PER_BEAT    ; 1     ; Signed Integer                                                                                                                                               ;
; BITS_PER_SYMBOL     ; 103   ; Signed Integer                                                                                                                                               ;
; FIFO_DEPTH          ; 2     ; Signed Integer                                                                                                                                               ;
; CHANNEL_WIDTH       ; 0     ; Signed Integer                                                                                                                                               ;
; ERROR_WIDTH         ; 0     ; Signed Integer                                                                                                                                               ;
; USE_PACKETS         ; 1     ; Signed Integer                                                                                                                                               ;
; USE_FILL_LEVEL      ; 0     ; Signed Integer                                                                                                                                               ;
; USE_STORE_FORWARD   ; 0     ; Signed Integer                                                                                                                                               ;
; USE_ALMOST_FULL_IF  ; 0     ; Signed Integer                                                                                                                                               ;
; USE_ALMOST_EMPTY_IF ; 0     ; Signed Integer                                                                                                                                               ;
; EMPTY_LATENCY       ; 1     ; Signed Integer                                                                                                                                               ;
; USE_MEMORY_BLOCKS   ; 0     ; Signed Integer                                                                                                                                               ;
; DATA_WIDTH          ; 103   ; Signed Integer                                                                                                                                               ;
; EMPTY_WIDTH         ; 0     ; Signed Integer                                                                                                                                               ;
+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                    ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 1     ; Signed Integer                                                                                                                                                                                          ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                          ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                          ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                          ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                              ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                    ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                    ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                    ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                    ;
+--------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router_001|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value ; Type                                                                                                                                                                                                  ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; DEFAULT_CHANNEL    ; 0     ; Signed Integer                                                                                                                                                                                        ;
; DEFAULT_WR_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                        ;
; DEFAULT_RD_CHANNEL ; -1    ; Signed Integer                                                                                                                                                                                        ;
; DEFAULT_DESTID     ; 0     ; Signed Integer                                                                                                                                                                                        ;
+--------------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+
; Parameter Name            ; Value ; Type                                                                                                         ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+
; PKT_TRANS_POSTED          ; 69    ; Signed Integer                                                                                               ;
; PKT_DEST_ID_H             ; 88    ; Signed Integer                                                                                               ;
; PKT_DEST_ID_L             ; 88    ; Signed Integer                                                                                               ;
; PKT_SRC_ID_H              ; 87    ; Signed Integer                                                                                               ;
; PKT_SRC_ID_L              ; 87    ; Signed Integer                                                                                               ;
; ST_DATA_W                 ; 102   ; Signed Integer                                                                                               ;
; ST_CHANNEL_W              ; 2     ; Signed Integer                                                                                               ;
; MAX_OUTSTANDING_RESPONSES ; 1     ; Signed Integer                                                                                               ;
; PIPELINED                 ; 0     ; Signed Integer                                                                                               ;
; ENFORCE_ORDER             ; 1     ; Signed Integer                                                                                               ;
; PKT_BYTE_CNT_H            ; 76    ; Signed Integer                                                                                               ;
; PKT_BYTE_CNT_L            ; 74    ; Signed Integer                                                                                               ;
; PKT_BYTEEN_H              ; 35    ; Signed Integer                                                                                               ;
; PKT_BYTEEN_L              ; 32    ; Signed Integer                                                                                               ;
; PKT_TRANS_WRITE           ; 70    ; Signed Integer                                                                                               ;
; PKT_TRANS_READ            ; 0     ; Signed Integer                                                                                               ;
; VALID_WIDTH               ; 2     ; Signed Integer                                                                                               ;
; PREVENT_HAZARDS           ; 0     ; Signed Integer                                                                                               ;
; REORDER                   ; 0     ; Signed Integer                                                                                               ;
+---------------------------+-------+--------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb ;
+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                              ;
+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; NUM_REQUESTERS ; 2      ; Signed Integer                                                                                                                                                    ;
; SCHEME         ; no-arb ; String                                                                                                                                                            ;
; PIPELINE       ; 0      ; Signed Integer                                                                                                                                                    ;
+----------------+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                             ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH          ; 4     ; Signed Integer                                                                                                                                                                                   ;
+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller ;
+---------------------------+----------+----------------------------------------------------------------+
; Parameter Name            ; Value    ; Type                                                           ;
+---------------------------+----------+----------------------------------------------------------------+
; NUM_RESET_INPUTS          ; 1        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN0     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN1     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN2     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN3     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN4     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN5     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN6     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN7     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN8     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN9     ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN10    ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN11    ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN12    ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN13    ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN14    ; 0        ; Signed Integer                                                 ;
; USE_RESET_REQUEST_IN15    ; 0        ; Signed Integer                                                 ;
; OUTPUT_RESET_SYNC_EDGES   ; deassert ; String                                                         ;
; SYNC_DEPTH                ; 2        ; Signed Integer                                                 ;
; RESET_REQUEST_PRESENT     ; 0        ; Signed Integer                                                 ;
; RESET_REQ_WAIT_TIME       ; 1        ; Signed Integer                                                 ;
; MIN_RST_ASSERTION_TIME    ; 3        ; Signed Integer                                                 ;
; RESET_REQ_EARLY_DSRT_TIME ; 1        ; Signed Integer                                                 ;
; ADAPT_RESET_REQUEST       ; 0        ; Signed Integer                                                 ;
+---------------------------+----------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 1     ; Unsigned Binary                                                                                                         ;
; DEPTH          ; 2     ; Signed Integer                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                        ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+
; ASYNC_RESET    ; 0     ; Signed Integer                                                                                                              ;
; DEPTH          ; 2     ; Signed Integer                                                                                                              ;
+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0 ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                             ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                          ;
; WIDTH_A                            ; 8                    ; Untyped                                                                          ;
; WIDTHAD_A                          ; 6                    ; Untyped                                                                          ;
; NUMWORDS_A                         ; 64                   ; Untyped                                                                          ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_B                            ; 8                    ; Untyped                                                                          ;
; WIDTHAD_B                          ; 6                    ; Untyped                                                                          ;
; NUMWORDS_B                         ; 64                   ; Untyped                                                                          ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                          ;
; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                                          ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                          ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                          ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                          ;
; INIT_FILE                          ; UNUSED               ; Untyped                                                                          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                          ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                          ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                          ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                                                          ;
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                                          ;
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                                          ;
; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                          ;
; CBXI_PARAMETER                     ; altsyncram_nog1      ; Untyped                                                                          ;
+------------------------------------+----------------------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                                                        ;
+-------------------------------------------+---------------------------------------------------------------------------------------------+
; Name                                      ; Value                                                                                       ;
+-------------------------------------------+---------------------------------------------------------------------------------------------+
; Number of entity instances                ; 1                                                                                           ;
; Entity Instance                           ; JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0 ;
;     -- OPERATION_MODE                     ; DUAL_PORT                                                                                   ;
;     -- WIDTH_A                            ; 8                                                                                           ;
;     -- NUMWORDS_A                         ; 64                                                                                          ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                ;
;     -- WIDTH_B                            ; 8                                                                                           ;
;     -- NUMWORDS_B                         ; 64                                                                                          ;
;     -- ADDRESS_REG_B                      ; CLOCK0                                                                                      ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                        ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                                                                                    ;
+-------------------------------------------+---------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|altera_reset_controller:rst_controller" ;
+----------------+--------+----------+-------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                         ;
+----------------+--------+----------+-------------------------------------------------+
; reset_req      ; Output ; Info     ; Explicitly unconnected                          ;
; reset_req_in0  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in1      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in1  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in2      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in2  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in3      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in3  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in4      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in4  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in5      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in5  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in6      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in6  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in7      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in7  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in8      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in8  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in9      ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in9  ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in10     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in10 ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in11     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in11 ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in12     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in12 ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in13     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in13 ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in14     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in14 ; Input  ; Info     ; Stuck at GND                                    ;
; reset_in15     ; Input  ; Info     ; Stuck at GND                                    ;
; reset_req_in15 ; Input  ; Info     ; Stuck at GND                                    ;
+----------------+--------+----------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                    ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; b[3..1] ; Input  ; Info     ; Stuck at GND                                                                                                                                                               ;
; b[0]    ; Input  ; Info     ; Stuck at VCC                                                                                                                                                               ;
; sum     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                        ;
+---------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode" ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port                   ; Type   ; Severity ; Details                                                                                                                                                          ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_destination_id ; Output ; Info     ; Explicitly unconnected                                                                                                                                           ;
; default_wr_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                           ;
; default_rd_channel     ; Output ; Info     ; Explicitly unconnected                                                                                                                                           ;
+------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode" ;
+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                    ;
+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; default_wr_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                     ;
; default_rd_channel ; Output ; Info     ; Explicitly unconnected                                                                                                                                                     ;
+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pin_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                           ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pin_s1_translator_avalon_universal_slave_0_agent" ;
+-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                                                                ;
+-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+
; m0_response             ; Input  ; Info     ; Stuck at GND                                                                                                           ;
; m0_writeresponserequest ; Output ; Info     ; Explicitly unconnected                                                                                                 ;
; m0_writeresponsevalid   ; Input  ; Info     ; Stuck at GND                                                                                                           ;
+-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                                                                                            ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; in_error          ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                                                                                                       ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                                                                                             ;
+-------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent" ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                                                                 ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------+
; m0_response             ; Input  ; Info     ; Stuck at GND                                                                                                            ;
; m0_writeresponserequest ; Output ; Info     ; Explicitly unconnected                                                                                                  ;
; m0_writeresponsevalid   ; Input  ; Info     ; Stuck at GND                                                                                                            ;
+-------------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent" ;
+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+
; Port                    ; Type   ; Severity ; Details                                                                                                                           ;
+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+
; av_response             ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
; av_writeresponserequest ; Input  ; Info     ; Stuck at GND                                                                                                                      ;
; av_writeresponsevalid   ; Output ; Info     ; Explicitly unconnected                                                                                                            ;
+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pin_s1_translator" ;
+--------------------------+--------+----------+---------------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                                     ;
+--------------------------+--------+----------+---------------------------------------------------------------------------------------------+
; av_write                 ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_read                  ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_writedata             ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_begintransfer         ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_beginbursttransfer    ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_burstcount            ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_byteenable            ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_readdatavalid         ; Input  ; Info     ; Stuck at GND                                                                                ;
; av_waitrequest           ; Input  ; Info     ; Stuck at GND                                                                                ;
; av_writebyteenable       ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_lock                  ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_chipselect            ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_clken                 ; Output ; Info     ; Explicitly unconnected                                                                      ;
; uav_clken                ; Input  ; Info     ; Stuck at GND                                                                                ;
; av_debugaccess           ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_outputenable          ; Output ; Info     ; Explicitly unconnected                                                                      ;
; uav_response             ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_response              ; Input  ; Info     ; Stuck at GND                                                                                ;
; uav_writeresponserequest ; Input  ; Info     ; Stuck at GND                                                                                ;
; uav_writeresponsevalid   ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_writeresponserequest  ; Output ; Info     ; Explicitly unconnected                                                                      ;
; av_writeresponsevalid    ; Input  ; Info     ; Stuck at GND                                                                                ;
+--------------------------+--------+----------+---------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator" ;
+--------------------------+--------+----------+----------------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                                      ;
+--------------------------+--------+----------+----------------------------------------------------------------------------------------------+
; av_read                  ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_begintransfer         ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_beginbursttransfer    ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_burstcount            ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_byteenable            ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_readdatavalid         ; Input  ; Info     ; Stuck at GND                                                                                 ;
; av_waitrequest           ; Input  ; Info     ; Stuck at GND                                                                                 ;
; av_writebyteenable       ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_lock                  ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_clken                 ; Output ; Info     ; Explicitly unconnected                                                                       ;
; uav_clken                ; Input  ; Info     ; Stuck at GND                                                                                 ;
; av_debugaccess           ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_outputenable          ; Output ; Info     ; Explicitly unconnected                                                                       ;
; uav_response             ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_response              ; Input  ; Info     ; Stuck at GND                                                                                 ;
; uav_writeresponserequest ; Input  ; Info     ; Stuck at GND                                                                                 ;
; uav_writeresponsevalid   ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_writeresponserequest  ; Output ; Info     ; Explicitly unconnected                                                                       ;
; av_writeresponsevalid    ; Input  ; Info     ; Stuck at GND                                                                                 ;
+--------------------------+--------+----------+----------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator" ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+
; Port                     ; Type   ; Severity ; Details                                                                                               ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+
; av_burstcount            ; Input  ; Info     ; Stuck at VCC                                                                                          ;
; av_beginbursttransfer    ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_begintransfer         ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_chipselect            ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_lock                  ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_debugaccess           ; Input  ; Info     ; Stuck at GND                                                                                          ;
; uav_clken                ; Output ; Info     ; Explicitly unconnected                                                                                ;
; av_clken                 ; Input  ; Info     ; Stuck at VCC                                                                                          ;
; uav_response             ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_response              ; Output ; Info     ; Explicitly unconnected                                                                                ;
; uav_writeresponserequest ; Output ; Info     ; Explicitly unconnected                                                                                ;
; uav_writeresponsevalid   ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_writeresponserequest  ; Input  ; Info     ; Stuck at GND                                                                                          ;
; av_writeresponsevalid    ; Output ; Info     ; Explicitly unconnected                                                                                ;
+--------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" ;
+----------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                         ;
+----------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+
; reset_in ; Input ; Info     ; Stuck at GND                                                                                                                    ;
+----------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller" ;
+----------------+--------+----------+---------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                   ;
+----------------+--------+----------+---------------------------------------------------------------------------+
; reset_req      ; Output ; Info     ; Explicitly unconnected                                                    ;
; reset_req_in0  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in1      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in1  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in2      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in2  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in3      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in3  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in4      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in4  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in5      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in5  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in6      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in6  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in7      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in7  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in8      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in8  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in9      ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in9  ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in10     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in10 ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in11     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in11 ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in12     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in12 ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in13     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in13 ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in14     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in14 ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_in15     ; Input  ; Info     ; Stuck at GND                                                              ;
; reset_req_in15 ; Input  ; Info     ; Stuck at GND                                                              ;
+----------------+--------+----------+---------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo" ;
+-------------------+--------+----------+------------------------------------------------------------+
; Port              ; Type   ; Severity ; Details                                                    ;
+-------------------+--------+----------+------------------------------------------------------------+
; csr_address       ; Input  ; Info     ; Stuck at GND                                               ;
; csr_read          ; Input  ; Info     ; Stuck at GND                                               ;
; csr_write         ; Input  ; Info     ; Stuck at GND                                               ;
; csr_readdata      ; Output ; Info     ; Explicitly unconnected                                     ;
; csr_writedata     ; Input  ; Info     ; Stuck at GND                                               ;
; almost_full_data  ; Output ; Info     ; Explicitly unconnected                                     ;
; almost_empty_data ; Output ; Info     ; Explicitly unconnected                                     ;
; in_startofpacket  ; Input  ; Info     ; Stuck at GND                                               ;
; in_endofpacket    ; Input  ; Info     ; Stuck at GND                                               ;
; out_startofpacket ; Output ; Info     ; Explicitly unconnected                                     ;
; out_endofpacket   ; Output ; Info     ; Explicitly unconnected                                     ;
; in_empty          ; Input  ; Info     ; Stuck at GND                                               ;
; out_empty         ; Output ; Info     ; Explicitly unconnected                                     ;
; in_error          ; Input  ; Info     ; Stuck at GND                                               ;
; out_error         ; Output ; Info     ; Explicitly unconnected                                     ;
; in_channel        ; Input  ; Info     ; Stuck at GND                                               ;
; out_channel       ; Output ; Info     ; Explicitly unconnected                                     ;
+-------------------+--------+----------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser" ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type  ; Severity ; Details                                                                                                                                                                                                                                  ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; sense_pos_edge ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                             ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter" ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port      ; Type   ; Severity ; Details                                                                                                                                                                                                                                      ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; out_valid ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                       ;
+-----------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover" ;
+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port      ; Type   ; Severity ; Details                                                                                                                                                                                                                                    ;
+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; in_ready  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                                                     ;
; out_ready ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                                                                               ;
+-----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" ;
+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                                                                                                                                                                                                               ;
+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tms             ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_tlr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_rti  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_sdrs ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_cdr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_sdr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_e1dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_pdr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_e2dr ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_udr  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_sirs ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_cir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_sir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_e1ir ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_pir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_e2ir ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
; jtag_state_uir  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                                                                                                                                              ;
+-----------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node" ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port               ; Type   ; Severity ; Details                                                                                                                                                                                                          ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; virtual_state_cir  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; virtual_state_e1dr ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; virtual_state_e2dr ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; virtual_state_pdr  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
; virtual_state_uir  ; Output ; Info     ; Explicitly unconnected                                                                                                                                                                                           ;
+--------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                                                                                                        ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; din  ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                                   ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_to_sample_div2_synchronizer" ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                      ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                                 ;
+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:reset_to_sample_synchronizer" ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                                 ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                            ;
+---------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sensor_synchronizer" ;
+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type  ; Severity ; Details                                                                                                                                                                                                                                              ;
+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; reset_n ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                                                                         ;
+---------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                                                                               ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; din  ; Input ; Info     ; Stuck at VCC                                                                                                                                                                                          ;
+------+-------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master"                                        ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port         ; Type   ; Severity ; Details                                                                                                                                      ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; source_ready ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
; debug_reset  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; mgmt_valid   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; mgmt_channel ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
; mgmt_data    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
+--------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0" ;
+--------------------+--------+----------+--------------------------------+
; Port               ; Type   ; Severity ; Details                        ;
+--------------------+--------+----------+--------------------------------+
; master_reset_reset ; Output ; Info     ; Explicitly unconnected         ;
+--------------------+--------+----------+--------------------------------+


+-------------------------------------------------+
; Port Connectivity Checks: "JTAG_MM:U_jtag_mm"   ;
+---------------+-------+----------+--------------+
; Port          ; Type  ; Severity ; Details      ;
+---------------+-------+----------+--------------+
; reset_reset_n ; Input ; Info     ; Stuck at VCC ;
+---------------+-------+----------+--------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:02     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Info: Processing started: Tue Jun 09 09:53:34 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file top.v
    Info (12023): Found entity 1: top
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/jtag_mm.v
    Info (12023): Found entity 1: JTAG_MM
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_reset_controller.v
    Info (12023): Found entity 1: altera_reset_controller
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_reset_synchronizer.v
    Info (12023): Found entity 1: altera_reset_synchronizer
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0.v
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0
Info (12021): Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_arbitrator.sv
    Info (12023): Found entity 1: altera_merlin_arbitrator
    Info (12023): Found entity 2: altera_merlin_arb_adder
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_mux.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_rsp_xbar_mux
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_rsp_xbar_demux.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_rsp_xbar_demux
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_mux.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_cmd_xbar_mux
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_cmd_xbar_demux.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_cmd_xbar_demux
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_traffic_limiter.sv
    Info (12023): Found entity 1: altera_merlin_traffic_limiter
Info (12021): Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_reorder_memory.sv
    Info (12023): Found entity 1: altera_merlin_reorder_memory
    Info (12023): Found entity 2: memory_pointer_controller
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_sc_fifo.v
    Info (12023): Found entity 1: altera_avalon_sc_fifo
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_pipeline_base.v
    Info (12023): Found entity 1: altera_avalon_st_pipeline_base
Info (12021): Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_id_router.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_id_router_default_decode
    Info (12023): Found entity 2: JTAG_MM_mm_interconnect_0_id_router
Info (12021): Found 2 design units, including 2 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_mm_interconnect_0_addr_router.sv
    Info (12023): Found entity 1: JTAG_MM_mm_interconnect_0_addr_router_default_decode
    Info (12023): Found entity 2: JTAG_MM_mm_interconnect_0_addr_router
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_slave_agent.sv
    Info (12023): Found entity 1: altera_merlin_slave_agent
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_burst_uncompressor.sv
    Info (12023): Found entity 1: altera_merlin_burst_uncompressor
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_master_agent.sv
    Info (12023): Found entity 1: altera_merlin_master_agent
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_slave_translator.sv
    Info (12023): Found entity 1: altera_merlin_slave_translator
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_merlin_master_translator.sv
    Info (12023): Found entity 1: altera_merlin_master_translator
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_pin.v
    Info (12023): Found entity 1: JTAG_MM_PIN
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_pout.v
    Info (12023): Found entity 1: JTAG_MM_POUT
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0.v
    Info (12023): Found entity 1: JTAG_MM_master_0
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_p2b_adapter.v
    Info (12023): Found entity 1: JTAG_MM_master_0_p2b_adapter
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_b2p_adapter.v
    Info (12023): Found entity 1: JTAG_MM_master_0_b2p_adapter
Info (12021): Found 7 design units, including 7 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_packets_to_master.v
    Info (12023): Found entity 1: altera_avalon_packets_to_master
    Info (12023): Found entity 2: packets_to_fifo
    Info (12023): Found entity 3: fifo_buffer_single_clock_fifo
    Info (12023): Found entity 4: fifo_buffer_scfifo_with_controls
    Info (12023): Found entity 5: fifo_buffer
    Info (12023): Found entity 6: fifo_to_packet
    Info (12023): Found entity 7: packets_to_master
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_packets_to_bytes.v
    Info (12023): Found entity 1: altera_avalon_st_packets_to_bytes
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_bytes_to_packets.v
    Info (12023): Found entity 1: altera_avalon_st_bytes_to_packets
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/jtag_mm_master_0_timing_adt.v
    Info (12023): Found entity 1: JTAG_MM_master_0_timing_adt
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_jtag_interface.v
    Info (12023): Found entity 1: altera_avalon_st_jtag_interface
Info (12021): Found 3 design units, including 3 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_dc_streaming.v
    Info (12023): Found entity 1: altera_jtag_control_signal_crosser
    Info (12023): Found entity 2: altera_jtag_src_crosser
    Info (12023): Found entity 3: altera_jtag_dc_streaming
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_sld_node.v
    Info (12023): Found entity 1: altera_jtag_sld_node
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_jtag_streaming.v
    Info (12023): Found entity 1: altera_jtag_streaming
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_pli_streaming.v
    Info (12023): Found entity 1: altera_pli_streaming
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_clock_crosser.v
    Info (12023): Found entity 1: altera_avalon_st_clock_crosser
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_idle_remover.v
    Info (12023): Found entity 1: altera_avalon_st_idle_remover
Info (12021): Found 1 design units, including 1 entities, in source file jtag_mm/synthesis/submodules/altera_avalon_st_idle_inserter.v
    Info (12023): Found entity 1: altera_avalon_st_idle_inserter
Info (12127): Elaborating entity "top" for the top level hierarchy
Info (12128): Elaborating entity "JTAG_MM" for hierarchy "JTAG_MM:U_jtag_mm"
Info (12128): Elaborating entity "JTAG_MM_master_0" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0"
Info (12128): Elaborating entity "altera_avalon_st_jtag_interface" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master"
Info (12128): Elaborating entity "altera_jtag_dc_streaming" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming"
Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer"
Info (12130): Elaborated megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer"
Info (12133): Instantiated megafunction "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_std_synchronizer:synchronizer" with the following parameter:
    Info (12134): Parameter "depth" = "3"
Info (12128): Elaborating entity "altera_jtag_streaming" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming"
Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer"
Info (12130): Elaborated megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer"
Info (12133): Instantiated megafunction "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_std_synchronizer:clock_sense_reset_n_synchronizer" with the following parameter:
    Info (12134): Parameter "depth" = "8"
Info (12128): Elaborating entity "altera_jtag_sld_node" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node"
Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component"
Info (12130): Elaborated megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component"
Info (12133): Instantiated megafunction "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component" with the following parameter:
    Info (12134): Parameter "sld_mfg_id" = "110"
    Info (12134): Parameter "sld_type_id" = "132"
    Info (12134): Parameter "sld_version" = "1"
    Info (12134): Parameter "sld_auto_instance_index" = "YES"
    Info (12134): Parameter "sld_instance_index" = "0"
    Info (12134): Parameter "sld_ir_width" = "3"
    Info (12134): Parameter "sld_sim_action" = ""
    Info (12134): Parameter "sld_sim_n_scan" = "0"
    Info (12134): Parameter "sld_sim_total_length" = "0"
Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst"
Info (12131): Elaborated megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component"
Info (12128): Elaborating entity "altera_avalon_st_idle_remover" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_remover:idle_remover"
Info (12128): Elaborating entity "altera_avalon_st_idle_inserter" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_avalon_st_idle_inserter:idle_inserter"
Info (12128): Elaborating entity "altera_avalon_st_clock_crosser" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser"
Info (12128): Elaborating entity "altera_avalon_st_pipeline_base" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_avalon_st_clock_crosser:sink_crosser|altera_avalon_st_pipeline_base:output_stage"
Info (12128): Elaborating entity "altera_jtag_src_crosser" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser"
Info (12128): Elaborating entity "altera_jtag_control_signal_crosser" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_src_crosser:source_crosser|altera_jtag_control_signal_crosser:crosser"
Info (12128): Elaborating entity "JTAG_MM_master_0_timing_adt" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_timing_adt:timing_adt"
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo"
Info (12128): Elaborating entity "altera_avalon_st_bytes_to_packets" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_bytes_to_packets:b2p"
Info (12128): Elaborating entity "altera_avalon_st_packets_to_bytes" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_st_packets_to_bytes:p2b"
Info (12128): Elaborating entity "altera_avalon_packets_to_master" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto"
Info (12128): Elaborating entity "packets_to_master" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_packets_to_master:transacto|packets_to_master:p2m"
Info (12128): Elaborating entity "JTAG_MM_master_0_b2p_adapter" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_b2p_adapter:b2p_adapter"
Warning (10036): Verilog HDL or VHDL warning at JTAG_MM_master_0_b2p_adapter.v(28): object "out_channel" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at JTAG_MM_master_0_b2p_adapter.v(40): truncated value with size 8 to match size of target (1)
Info (12128): Elaborating entity "JTAG_MM_master_0_p2b_adapter" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|JTAG_MM_master_0_p2b_adapter:p2b_adapter"
Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller"
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1"
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1"
Info (12128): Elaborating entity "JTAG_MM_POUT" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_POUT:pout"
Info (12128): Elaborating entity "JTAG_MM_PIN" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_PIN:pin"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0"
Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:master_0_master_translator"
Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:pout_s1_translator"
Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:master_0_master_translator_avalon_universal_master_0_agent"
Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent"
Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:pout_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor"
Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:pout_s1_translator_avalon_universal_slave_0_agent_rsp_fifo"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_addr_router" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_addr_router_default_decode" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_addr_router:addr_router|JTAG_MM_mm_interconnect_0_addr_router_default_decode:the_default_decode"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_id_router" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_id_router_default_decode" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_id_router:id_router|JTAG_MM_mm_interconnect_0_id_router_default_decode:the_default_decode"
Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:limiter"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_cmd_xbar_demux" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_cmd_xbar_mux" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_rsp_xbar_demux" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_demux:rsp_xbar_demux"
Info (12128): Elaborating entity "JTAG_MM_mm_interconnect_0_rsp_xbar_mux" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux"
Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb"
Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "JTAG_MM:U_jtag_mm|JTAG_MM_mm_interconnect_0:mm_interconnect_0|JTAG_MM_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder"
Info (19000): Inferred 1 megafunctions from design logic
    Info (276029): Inferred altsyncram megafunction from the following design logic: "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|mem_rtl_0" 
        Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
        Info (286033): Parameter WIDTH_A set to 8
        Info (286033): Parameter WIDTHAD_A set to 6
        Info (286033): Parameter NUMWORDS_A set to 64
        Info (286033): Parameter WIDTH_B set to 8
        Info (286033): Parameter WIDTHAD_B set to 6
        Info (286033): Parameter NUMWORDS_B set to 64
        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
        Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
        Info (286033): Parameter ADDRESS_ACLR_B set to NONE
        Info (286033): Parameter OUTDATA_ACLR_B set to NONE
        Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
        Info (286033): Parameter INDATA_ACLR_A set to NONE
        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
        Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (12130): Elaborated megafunction instantiation "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "JTAG_MM:U_jtag_mm|JTAG_MM_master_0:master_0|altera_avalon_sc_fifo:fifo|altsyncram:mem_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
    Info (12134): Parameter "WIDTH_A" = "8"
    Info (12134): Parameter "WIDTHAD_A" = "6"
    Info (12134): Parameter "NUMWORDS_A" = "64"
    Info (12134): Parameter "WIDTH_B" = "8"
    Info (12134): Parameter "WIDTHAD_B" = "6"
    Info (12134): Parameter "NUMWORDS_B" = "64"
    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
    Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
    Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
    Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
    Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
    Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nog1.tdf
    Info (12023): Found entity 1: altsyncram_nog1
Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286031): Timing-Driven Synthesis is running on partition "Top"
Info (17049): 37 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 1050 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 14 input pins
    Info (21059): Implemented 11 output pins
    Info (21061): Implemented 1016 logic cells
    Info (21064): Implemented 8 RAM segments
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 553 megabytes
    Info: Processing ended: Tue Jun 09 09:53:40 2015
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:06


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in d:/current/MATLAB_FPGA_LAB/LAB3_M_JtagMM/hdl/prj_q131/output_files/top.map.smsg.


