# Reading C:/modeltech_10.0c/tcl/vsim/pref.tcl 
# //  ModelSim SE 10.0c Jul 21 2011 
# //
# //  Copyright 1991-2011 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# OpenFile D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/tb_ram_fir.mpf 
# Loading project tb_ram_fir
#  
# reading C:\modeltech_10.0c\win32/../modelsim.ini
# Loading project testbench
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim -novopt +nowarnTSCALE work.testbench
# vsim +nowarnTSCALE -novopt work.testbench 
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
# ** Error: (vsim-10000) D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v(52): Unresolved defparam reference to 'DUT_OUTWL' in U_dut_in.DUT_OUTWL.
#         Region: /testbench
# Error loading design
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim -novopt +nowarnTSCALE work.testbench
# vsim +nowarnTSCALE -novopt work.testbench 
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
add wave -position end  sim:/testbench/U_dut_out/CLK
add wave -position end  sim:/testbench/U_dut_out/RST
add wave -position end  sim:/testbench/U_dut_out/DUTOV
add wave -position end  sim:/testbench/U_dut_out/DUTOUT
add wave -position end  sim:/testbench/U_dut_out/CNT
add wave -position end  sim:/testbench/U_dut_out/dutov_d1R
add wave -position end  sim:/testbench/U_dut_out/wa_cnt_R1
add wave -position end  sim:/testbench/U_dut_out/wa_cnt_R2
add wave -position end  sim:/testbench/U_dut_out/dut_outR
add wave -position end  sim:/testbench/U_dut_out/wa_W
add wave -position end  sim:/testbench/U_dut_out/we_W
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by:   Hostname:   ProcessID: 3
#           Attempting to use alternate WLF file "./wlft7iqten".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlft7iqten
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 33
add wave -position end  sim:/testbench/U_dut_in/CLK
add wave -position end  sim:/testbench/U_dut_in/RST
add wave -position end  sim:/testbench/U_dut_in/DUT_DINEN
add wave -position end  sim:/testbench/U_dut_in/DUT_DIN
add wave -position end  sim:/testbench/U_dut_in/rom_rdW
add wave -position end  sim:/testbench/U_dut_in/cycle_cnt_R
add wave -position end  sim:/testbench/U_dut_in/cycle_cnt_ov
add wave -position end  sim:/testbench/U_dut_in/cycle_cnt_ov_d1R
add wave -position end  sim:/testbench/U_dut_in/cycle_cnt_ov_d2R
add wave -position end  sim:/testbench/U_dut_in/send_cnt_R
add wave -position end  sim:/testbench/U_dut_in/send_cnt_d1R
add wave -position end  sim:/testbench/U_dut_in/mode_W
add wave -position end  sim:/testbench/U_dut_in/rom_raW
restart
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 33
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 33
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 33
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 33
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v failed with 1 errors.
# 3 compiles, 1 failed with 1 error. 
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 45
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 45
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 45
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 42
add wave  \
sim:/testbench/DUTOV \
sim:/testbench/DUTOUT
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
restart
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f {} -noaddress /testbench/U_dut_out/U_dpram/mem
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f {} -noaddress -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
restart
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 /testbench/U_dut_out/U_dpram/mem
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
# Compile of dut_in_out.v was successful.
# Compile of DUT_IN_ROM.v was successful.
# Compile of testbench.v was successful.
# 3 compiles, 0 failed with no errors. 
restart
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.testbench
# Loading work.testbench
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.gen_clk_rst
# Loading work.gen_clk_rst
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_in_data
# Loading work.dut_in_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.DUT_IN_ROM
# Loading work.DUT_IN_ROM
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_data
# Loading work.dut_out_data
# Refreshing D:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim\work.dut_out_dpram
# Loading work.dut_out_dpram
run -all
# module dut_out_dpram().RAMInit()called @ 0
# Break in Module testbench at D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v line 40
mem save -o D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/modelsim/dout.mem -f mti -noaddress -data decimal -addr hex -startaddress 0 -endaddress 1023 -wordsperline 1 /testbench/U_dut_out/U_dpram/mem
