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Z0 dD:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim
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=1-4437e6a4cdf2-50e3feb1-72-4278
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n@_opt
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Z1 dD:\ECDAV_course\EDU_LAB\FPGA_LAB\fir_lab\ram_fir\hdl\modelsim
vdut_in_data
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31
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Z2 dD:\ECDAV_course\EDU_LAB\FPGA_LAB\dut_in_out_lab\hdl\modelsim
Z3 w1359623933
Z4 8D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/dut_in_out.v
Z5 FD:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/dut_in_out.v
L0 7
Z6 OE;L;10.0c;49
Z7 !s108 1359794595.021000
Z8 !s107 D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/dut_in_out.v|
Z9 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/dut_in_out.v|
Z10 !s102 -nocovercells
Z11 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
!s85 0
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L0 8
R6
R10
R11
n@d@u@t_@i@n_@r@o@m
!s85 0
!s100 [<V3B=5j33]T?QOKH061K3
!s90 -reportprogress|300|-work|work|-vopt|-nocovercells|D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/DUT_IN_ROM.v|
!s108 1359794595.239000
!s107 D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/DUT_IN_ROM.v|
vdut_out_data
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r1
31
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R2
R3
R4
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L0 131
R6
R7
R8
R9
R10
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!s85 0
!s100 h?ll8^J5CLl<_NikO>J1W1
vdut_out_dpram
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31
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R3
R4
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L0 198
R6
R7
R8
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R10
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Z13 8D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v
Z14 FD:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v
L0 85
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Z15 !s108 1359794595.369000
Z16 !s107 D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v|
Z17 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|D:/ECDAV_course/EDU_LAB/FPGA_LAB/dut_in_out_lab/hdl/src/testbench.v|
R10
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vram_fir
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31
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L0 2
R6
R10
R11
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!s90 -reportprogress|300|-work|work|-vopt|-nocovercells|D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/ram_fir.v|
!s108 1359020403.538000
!s107 D:/ECDAV_course/EDU_LAB/FPGA_LAB/fir_lab/ram_fir/hdl/src/ram_fir.v|
!s85 0
vtestbench
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r1
31
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R2
R12
R13
R14
L0 5
R6
R15
R16
R17
R10
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!s85 0
!s100 1<<AUz4M17:6n6cV^hiZ:1
