!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.7	//
AIC31ADCInit	aic31.c	/^void AIC31ADCInit(unsigned int baseAddr) $/;"	f
AIC31DACInit	aic31.c	/^void AIC31DACInit(unsigned int baseAddr)$/;"	f
AIC31DataConfig	aic31.c	/^void AIC31DataConfig(unsigned int baseAddr, unsigned char dataType, $/;"	f
AIC31I2SConfigure	board.c	/^void AIC31I2SConfigure(void)$/;"	f
AIC31Reset	aic31.c	/^void AIC31Reset(unsigned int baseAddr)$/;"	f
AIC31SampleRateConfig	aic31.c	/^void AIC31SampleRateConfig(unsigned int baseAddr, unsigned int mode, $/;"	f
AIC31_DATATYPE_DSP	aic31.h	50;"	d
AIC31_DATATYPE_I2S	aic31.h	49;"	d
AIC31_DATATYPE_LEFTJ	aic31.h	52;"	d
AIC31_DATATYPE_RIGHTJ	aic31.h	51;"	d
AIC31_MODE_ADC	aic31.h	57;"	d
AIC31_MODE_BOTH	aic31.h	59;"	d
AIC31_MODE_DAC	aic31.h	58;"	d
AIC31_P0_REG0	aic31.c	48;"	d	file:
AIC31_P0_REG1	aic31.c	49;"	d	file:
AIC31_P0_REG10	aic31.c	58;"	d	file:
AIC31_P0_REG100	aic31.c	147;"	d	file:
AIC31_P0_REG101	aic31.c	148;"	d	file:
AIC31_P0_REG102	aic31.c	149;"	d	file:
AIC31_P0_REG11	aic31.c	59;"	d	file:
AIC31_P0_REG12	aic31.c	60;"	d	file:
AIC31_P0_REG13	aic31.c	61;"	d	file:
AIC31_P0_REG14	aic31.c	62;"	d	file:
AIC31_P0_REG15	aic31.c	63;"	d	file:
AIC31_P0_REG16	aic31.c	64;"	d	file:
AIC31_P0_REG17	aic31.c	65;"	d	file:
AIC31_P0_REG18	aic31.c	66;"	d	file:
AIC31_P0_REG19	aic31.c	67;"	d	file:
AIC31_P0_REG2	aic31.c	50;"	d	file:
AIC31_P0_REG20	aic31.c	68;"	d	file:
AIC31_P0_REG21	aic31.c	69;"	d	file:
AIC31_P0_REG22	aic31.c	70;"	d	file:
AIC31_P0_REG23	aic31.c	71;"	d	file:
AIC31_P0_REG24	aic31.c	72;"	d	file:
AIC31_P0_REG25	aic31.c	73;"	d	file:
AIC31_P0_REG26	aic31.c	74;"	d	file:
AIC31_P0_REG27	aic31.c	75;"	d	file:
AIC31_P0_REG28	aic31.c	76;"	d	file:
AIC31_P0_REG29	aic31.c	77;"	d	file:
AIC31_P0_REG3	aic31.c	51;"	d	file:
AIC31_P0_REG30	aic31.c	78;"	d	file:
AIC31_P0_REG31	aic31.c	79;"	d	file:
AIC31_P0_REG32	aic31.c	80;"	d	file:
AIC31_P0_REG33	aic31.c	81;"	d	file:
AIC31_P0_REG34	aic31.c	82;"	d	file:
AIC31_P0_REG35	aic31.c	83;"	d	file:
AIC31_P0_REG36	aic31.c	84;"	d	file:
AIC31_P0_REG37	aic31.c	85;"	d	file:
AIC31_P0_REG38	aic31.c	86;"	d	file:
AIC31_P0_REG4	aic31.c	52;"	d	file:
AIC31_P0_REG40	aic31.c	87;"	d	file:
AIC31_P0_REG41	aic31.c	88;"	d	file:
AIC31_P0_REG42	aic31.c	89;"	d	file:
AIC31_P0_REG43	aic31.c	90;"	d	file:
AIC31_P0_REG44	aic31.c	91;"	d	file:
AIC31_P0_REG45	aic31.c	92;"	d	file:
AIC31_P0_REG46	aic31.c	93;"	d	file:
AIC31_P0_REG47	aic31.c	94;"	d	file:
AIC31_P0_REG48	aic31.c	95;"	d	file:
AIC31_P0_REG49	aic31.c	96;"	d	file:
AIC31_P0_REG5	aic31.c	53;"	d	file:
AIC31_P0_REG50	aic31.c	97;"	d	file:
AIC31_P0_REG51	aic31.c	98;"	d	file:
AIC31_P0_REG52	aic31.c	99;"	d	file:
AIC31_P0_REG53	aic31.c	100;"	d	file:
AIC31_P0_REG54	aic31.c	101;"	d	file:
AIC31_P0_REG55	aic31.c	102;"	d	file:
AIC31_P0_REG56	aic31.c	103;"	d	file:
AIC31_P0_REG57	aic31.c	104;"	d	file:
AIC31_P0_REG58	aic31.c	105;"	d	file:
AIC31_P0_REG59	aic31.c	106;"	d	file:
AIC31_P0_REG6	aic31.c	54;"	d	file:
AIC31_P0_REG60	aic31.c	107;"	d	file:
AIC31_P0_REG61	aic31.c	108;"	d	file:
AIC31_P0_REG62	aic31.c	109;"	d	file:
AIC31_P0_REG63	aic31.c	110;"	d	file:
AIC31_P0_REG64	aic31.c	111;"	d	file:
AIC31_P0_REG65	aic31.c	112;"	d	file:
AIC31_P0_REG66	aic31.c	113;"	d	file:
AIC31_P0_REG67	aic31.c	114;"	d	file:
AIC31_P0_REG68	aic31.c	115;"	d	file:
AIC31_P0_REG69	aic31.c	116;"	d	file:
AIC31_P0_REG7	aic31.c	55;"	d	file:
AIC31_P0_REG70	aic31.c	117;"	d	file:
AIC31_P0_REG71	aic31.c	118;"	d	file:
AIC31_P0_REG72	aic31.c	119;"	d	file:
AIC31_P0_REG73	aic31.c	120;"	d	file:
AIC31_P0_REG74	aic31.c	121;"	d	file:
AIC31_P0_REG75	aic31.c	122;"	d	file:
AIC31_P0_REG76	aic31.c	123;"	d	file:
AIC31_P0_REG77	aic31.c	124;"	d	file:
AIC31_P0_REG78	aic31.c	125;"	d	file:
AIC31_P0_REG79	aic31.c	126;"	d	file:
AIC31_P0_REG8	aic31.c	56;"	d	file:
AIC31_P0_REG80	aic31.c	127;"	d	file:
AIC31_P0_REG81	aic31.c	128;"	d	file:
AIC31_P0_REG82	aic31.c	129;"	d	file:
AIC31_P0_REG83	aic31.c	130;"	d	file:
AIC31_P0_REG84	aic31.c	131;"	d	file:
AIC31_P0_REG85	aic31.c	132;"	d	file:
AIC31_P0_REG86	aic31.c	133;"	d	file:
AIC31_P0_REG87	aic31.c	134;"	d	file:
AIC31_P0_REG88	aic31.c	135;"	d	file:
AIC31_P0_REG89	aic31.c	136;"	d	file:
AIC31_P0_REG9	aic31.c	57;"	d	file:
AIC31_P0_REG90	aic31.c	137;"	d	file:
AIC31_P0_REG91	aic31.c	138;"	d	file:
AIC31_P0_REG92	aic31.c	139;"	d	file:
AIC31_P0_REG93	aic31.c	140;"	d	file:
AIC31_P0_REG94	aic31.c	141;"	d	file:
AIC31_P0_REG95	aic31.c	142;"	d	file:
AIC31_P0_REG96	aic31.c	143;"	d	file:
AIC31_P0_REG97	aic31.c	144;"	d	file:
AIC31_P0_REG98	aic31.c	145;"	d	file:
AIC31_P0_REG99	aic31.c	146;"	d	file:
AIC31_RESET	aic31.c	151;"	d	file:
AIC31_SLOT_WIDTH_16	aic31.c	153;"	d	file:
AIC31_SLOT_WIDTH_20	aic31.c	154;"	d	file:
AIC31_SLOT_WIDTH_24	aic31.c	155;"	d	file:
AIC31_SLOT_WIDTH_32	aic31.c	156;"	d	file:
AUDIO_BUF_SIZE	board.h	66;"	d
BYTES_PER_SAMPLE	board.h	54;"	d
CFGCHIP0	C6748_gel_reg.h	263;"	d
CFGCHIP2	C6748_gel_reg.h	264;"	d
CFGCHIP3	C6748_gel_reg.h	265;"	d
CODEC_INTERFACE_I2C	codecif.h	48;"	d
CodecRegBitClr	codecif.c	/^void CodecRegBitClr(unsigned int baseAddr, unsigned char regAddr,    $/;"	f
CodecRegBitSet	codecif.c	/^void CodecRegBitSet(unsigned int baseAddr, unsigned char regAddr, $/;"	f
CodecRegRead	codecif.c	/^unsigned char CodecRegRead(unsigned int baseAddr, unsigned char regAddr)$/;"	f
CodecRegWrite	codecif.c	/^void CodecRegWrite(unsigned int baseAddr, unsigned char regAddr,$/;"	f
DDR2	C6748_gel_reg.h	195;"	d
DDRPHYREV	C6748_gel_reg.h	192;"	d
DDR_DEBUG	C6748_gel_reg.h	198;"	d
DEVICE_DDRConfig	C6748_gel.c	/^void DEVICE_DDRConfig(unsigned int ddr_type, unsigned int freq)$/;"	f
DRPYC1R	C6748_gel_reg.h	193;"	d
EDMA3CCComplIsr	board.c	/^void EDMA3CCComplIsr(void) {$/;"	f
EDMA3IntSetup	board.c	/^void EDMA3IntSetup(void)$/;"	f
EDMA_I2S_init	board.c	/^void EDMA_I2S_init(){$/;"	f
EMIFA	C6748_gel_reg.h	208;"	d
EMIFA_ACFG2	C6748_gel_reg.h	213;"	d
EMIFA_ACFG3	C6748_gel_reg.h	214;"	d
EMIFA_ACFG4	C6748_gel_reg.h	215;"	d
EMIFA_ACFG5	C6748_gel_reg.h	216;"	d
EMIFA_AWAITCFG	C6748_gel_reg.h	210;"	d
EMIFA_BASE_ADDR	C6748_gel_reg.h	201;"	d
EMIFA_CS2_BASE_ADDR	C6748_gel_reg.h	202;"	d
EMIFA_CS3_BASE_ADDR	C6748_gel_reg.h	203;"	d
EMIFA_CS4_BASE_ADDR	C6748_gel_reg.h	204;"	d
EMIFA_CS5_BASE_ADDR	C6748_gel_reg.h	205;"	d
EMIFA_NANDFCR	C6748_gel_reg.h	219;"	d
EMIFA_SDCFG	C6748_gel_reg.h	211;"	d
EMIFA_SDREF	C6748_gel_reg.h	212;"	d
EMIFA_SDTIM	C6748_gel_reg.h	217;"	d
EMIFA_SRPD	C6748_gel_reg.h	218;"	d
EMIFDDR_BASE_ADDR	C6748_gel_reg.h	200;"	d
EMIFDDR_IMCR	C6748_gel_reg.h	191;"	d
EMIFDDR_IMR	C6748_gel_reg.h	189;"	d
EMIFDDR_IMSR	C6748_gel_reg.h	190;"	d
EMIFDDR_IRR	C6748_gel_reg.h	188;"	d
EMIFDDR_PBBPR	C6748_gel_reg.h	185;"	d
EMIFDDR_REVID	C6748_gel_reg.h	178;"	d
EMIFDDR_SDCR	C6748_gel_reg.h	180;"	d
EMIFDDR_SDCR2	C6748_gel_reg.h	184;"	d
EMIFDDR_SDRAM_CFG	C6748_gel_reg.h	177;"	d
EMIFDDR_SDRCR	C6748_gel_reg.h	181;"	d
EMIFDDR_SDRSTAT	C6748_gel_reg.h	179;"	d
EMIFDDR_SDTIMR1	C6748_gel_reg.h	182;"	d
EMIFDDR_SDTIMR2	C6748_gel_reg.h	183;"	d
EMIFDDR_VBUSMCFG1	C6748_gel_reg.h	186;"	d
EMIFDDR_VBUSMCFG2	C6748_gel_reg.h	187;"	d
GPIO_BANK01_BASE	C6748_gel_reg.h	228;"	d
GPIO_BANK23_BASE	C6748_gel_reg.h	229;"	d
GPIO_BANK23_CLR	C6748_gel_reg.h	236;"	d
GPIO_BANK23_DAT	C6748_gel_reg.h	234;"	d
GPIO_BANK23_DIR	C6748_gel_reg.h	233;"	d
GPIO_BANK23_SET	C6748_gel_reg.h	235;"	d
GPIO_BANK45_BASE	C6748_gel_reg.h	230;"	d
GPIO_BANK67_BASE	C6748_gel_reg.h	231;"	d
GPIO_BANK8_BASE	C6748_gel_reg.h	232;"	d
GPIO_BANK_OFFSET	C6748_gel_reg.h	223;"	d
GPIO_BINTEN	C6748_gel_reg.h	227;"	d
GPIO_CLR_OFFSET	C6748_gel_reg.h	226;"	d
GPIO_DAT_OFFSET	C6748_gel_reg.h	224;"	d
GPIO_REG_BASE	C6748_gel_reg.h	222;"	d
GPIO_SET_OFFSET	C6748_gel_reg.h	225;"	d
HOST0CFG	C6748_gel_reg.h	240;"	d
I2C0_AIC31_init	board.c	/^void I2C0_AIC31_init(){$/;"	f
I2CCodecIfInit	codecif.c	/^void I2CCodecIfInit(unsigned int baseAddr, unsigned int intCh, $/;"	f
I2CCodecIntSetup	codecif.c	/^static void I2CCodecIntSetup(unsigned int sysIntNum, unsigned int channel)$/;"	f	file:
I2CCodecIsr	codecif.c	/^void I2CCodecIsr(void)$/;"	f
I2CCodecRcvBlocking	codecif.c	/^static void I2CCodecRcvBlocking(unsigned int baseAddr, unsigned int dataCnt)$/;"	f	file:
I2CCodecSendBlocking	codecif.c	/^static void I2CCodecSendBlocking(unsigned int baseAddr, unsigned int dataCnt)$/;"	f	file:
I2C_SLAVE_CODEC_AIC31	board.h	37;"	d
I2SDMAParamInit	board.c	/^void I2SDMAParamInit(void)$/;"	f
I2SDataTxRxActivate	board.c	/^void I2SDataTxRxActivate(void)$/;"	f
I2S_SLOTS	board.h	53;"	d
INT_CHANNEL_EDMACC	board.h	42;"	d
INT_CHANNEL_I2C	board.h	40;"	d
INT_CHANNEL_MCASP	board.h	41;"	d
KICK0R	C6748_gel_reg.h	241;"	d
KICK1R	C6748_gel_reg.h	242;"	d
LPSC_ARM	C6748_gel_reg.h	140;"	d
LPSC_ARM_AINTC	C6748_gel_reg.h	132;"	d
LPSC_ARM_RAMROM	C6748_gel_reg.h	133;"	d
LPSC_BR_F7	C6748_gel_reg.h	172;"	d
LPSC_DDR	C6748_gel_reg.h	149;"	d
LPSC_DSP	C6748_gel_reg.h	141;"	d
LPSC_ECAP	C6748_gel_reg.h	163;"	d
LPSC_EDMA_CC0	C6748_gel_reg.h	126;"	d
LPSC_EDMA_CC1	C6748_gel_reg.h	143;"	d
LPSC_EDMA_TC0	C6748_gel_reg.h	127;"	d
LPSC_EDMA_TC1	C6748_gel_reg.h	128;"	d
LPSC_EDMA_TC2	C6748_gel_reg.h	164;"	d
LPSC_EMAC	C6748_gel_reg.h	148;"	d
LPSC_EMIFA	C6748_gel_reg.h	129;"	d
LPSC_EPWM	C6748_gel_reg.h	160;"	d
LPSC_GPIO	C6748_gel_reg.h	146;"	d
LPSC_I2C1	C6748_gel_reg.h	154;"	d
LPSC_LCDC	C6748_gel_reg.h	159;"	d
LPSC_MCASP0	C6748_gel_reg.h	150;"	d
LPSC_MCBSP0	C6748_gel_reg.h	157;"	d
LPSC_MCBSP1	C6748_gel_reg.h	158;"	d
LPSC_MMCSD0	C6748_gel_reg.h	131;"	d
LPSC_MMCSD1	C6748_gel_reg.h	161;"	d
LPSC_SATA	C6748_gel_reg.h	151;"	d
LPSC_SCR0	C6748_gel_reg.h	136;"	d
LPSC_SCR1	C6748_gel_reg.h	137;"	d
LPSC_SCR2	C6748_gel_reg.h	138;"	d
LPSC_SCR_F0	C6748_gel_reg.h	166;"	d
LPSC_SCR_F1	C6748_gel_reg.h	167;"	d
LPSC_SCR_F2	C6748_gel_reg.h	168;"	d
LPSC_SCR_F6	C6748_gel_reg.h	169;"	d
LPSC_SCR_F7	C6748_gel_reg.h	170;"	d
LPSC_SCR_F8	C6748_gel_reg.h	171;"	d
LPSC_SHARED_RAM	C6748_gel_reg.h	173;"	d
LPSC_SPI0	C6748_gel_reg.h	130;"	d
LPSC_SPI1	C6748_gel_reg.h	153;"	d
LPSC_UART0	C6748_gel_reg.h	135;"	d
LPSC_UART1	C6748_gel_reg.h	155;"	d
LPSC_UART2	C6748_gel_reg.h	156;"	d
LPSC_UHPI	C6748_gel_reg.h	147;"	d
LPSC_UPP	C6748_gel_reg.h	162;"	d
LPSC_USB11	C6748_gel_reg.h	145;"	d
LPSC_USB20	C6748_gel_reg.h	144;"	d
LPSC_VPIF	C6748_gel_reg.h	152;"	d
MCASP_XSER_RX	board.h	59;"	d
MCASP_XSER_TX	board.h	61;"	d
MDDR	C6748_gel_reg.h	196;"	d
McASPErrorIntSetup	board.c	/^void McASPErrorIntSetup(void)$/;"	f
McASPErrorIsr	board.c	/^void McASPErrorIsr(void)$/;"	f
McASPI2SConfigure	board.c	/^void McASPI2SConfigure(void)$/;"	f
McASPTxDMAComplHandler	board.c	/^void McASPTxDMAComplHandler(void)$/;"	f
McASP_init	board.c	/^void McASP_init(){$/;"	f
NUM_BUF	board.h	68;"	d
NUM_I2S_CHANNELS	board.h	52;"	d
NUM_PAR	board.h	76;"	d
NUM_SAMPLES_PER_AUDIO_BUF	board.h	64;"	d
PAR_ID_START	board.h	78;"	d
PAR_RX_START	board.h	73;"	d
PAR_TX_START	board.h	74;"	d
PD0	C6748_gel_reg.h	266;"	d
PD1	C6748_gel_reg.h	267;"	d
PINMUX0	C6748_gel_reg.h	243;"	d
PINMUX1	C6748_gel_reg.h	244;"	d
PINMUX10	C6748_gel_reg.h	253;"	d
PINMUX11	C6748_gel_reg.h	254;"	d
PINMUX12	C6748_gel_reg.h	255;"	d
PINMUX13	C6748_gel_reg.h	256;"	d
PINMUX14	C6748_gel_reg.h	257;"	d
PINMUX15	C6748_gel_reg.h	258;"	d
PINMUX16	C6748_gel_reg.h	259;"	d
PINMUX17	C6748_gel_reg.h	260;"	d
PINMUX18	C6748_gel_reg.h	261;"	d
PINMUX19	C6748_gel_reg.h	262;"	d
PINMUX2	C6748_gel_reg.h	245;"	d
PINMUX3	C6748_gel_reg.h	246;"	d
PINMUX4	C6748_gel_reg.h	247;"	d
PINMUX5	C6748_gel_reg.h	248;"	d
PINMUX6	C6748_gel_reg.h	249;"	d
PINMUX7	C6748_gel_reg.h	250;"	d
PINMUX8	C6748_gel_reg.h	251;"	d
PINMUX9	C6748_gel_reg.h	252;"	d
PLL0_ALNCTL	C6748_gel_reg.h	20;"	d
PLL0_BASE	C6748_gel_reg.h	3;"	d
PLL0_BPDIV	C6748_gel_reg.h	16;"	d
PLL0_CKEN	C6748_gel_reg.h	22;"	d
PLL0_CKSTAT	C6748_gel_reg.h	23;"	d
PLL0_DCHANGE	C6748_gel_reg.h	21;"	d
PLL0_OCSEL	C6748_gel_reg.h	7;"	d
PLL0_OSCDIV1	C6748_gel_reg.h	14;"	d
PLL0_PID	C6748_gel_reg.h	4;"	d
PLL0_PLLCMD	C6748_gel_reg.h	18;"	d
PLL0_PLLCTL	C6748_gel_reg.h	6;"	d
PLL0_PLLDIV1	C6748_gel_reg.h	11;"	d
PLL0_PLLDIV10	C6748_gel_reg.h	31;"	d
PLL0_PLLDIV11	C6748_gel_reg.h	32;"	d
PLL0_PLLDIV12	C6748_gel_reg.h	33;"	d
PLL0_PLLDIV13	C6748_gel_reg.h	34;"	d
PLL0_PLLDIV14	C6748_gel_reg.h	35;"	d
PLL0_PLLDIV15	C6748_gel_reg.h	36;"	d
PLL0_PLLDIV16	C6748_gel_reg.h	37;"	d
PLL0_PLLDIV2	C6748_gel_reg.h	12;"	d
PLL0_PLLDIV3	C6748_gel_reg.h	13;"	d
PLL0_PLLDIV4	C6748_gel_reg.h	25;"	d
PLL0_PLLDIV5	C6748_gel_reg.h	26;"	d
PLL0_PLLDIV6	C6748_gel_reg.h	27;"	d
PLL0_PLLDIV7	C6748_gel_reg.h	28;"	d
PLL0_PLLDIV8	C6748_gel_reg.h	29;"	d
PLL0_PLLDIV9	C6748_gel_reg.h	30;"	d
PLL0_PLLM	C6748_gel_reg.h	9;"	d
PLL0_PLLSTAT	C6748_gel_reg.h	19;"	d
PLL0_POSTDIV	C6748_gel_reg.h	15;"	d
PLL0_PREDIV	C6748_gel_reg.h	10;"	d
PLL0_RSTYPE	C6748_gel_reg.h	5;"	d
PLL0_SECCTL	C6748_gel_reg.h	8;"	d
PLL0_SYSTAT	C6748_gel_reg.h	24;"	d
PLL0_WAKEUP	C6748_gel_reg.h	17;"	d
PLL1_ALNCTL	C6748_gel_reg.h	56;"	d
PLL1_ALNCTL	C6748_gel_reg.h	91;"	d
PLL1_BASE	C6748_gel_reg.h	39;"	d
PLL1_BASE	C6748_gel_reg.h	74;"	d
PLL1_BPDIV	C6748_gel_reg.h	52;"	d
PLL1_BPDIV	C6748_gel_reg.h	87;"	d
PLL1_CKEN	C6748_gel_reg.h	58;"	d
PLL1_CKEN	C6748_gel_reg.h	93;"	d
PLL1_CKSTAT	C6748_gel_reg.h	59;"	d
PLL1_CKSTAT	C6748_gel_reg.h	94;"	d
PLL1_DCHANGE	C6748_gel_reg.h	57;"	d
PLL1_DCHANGE	C6748_gel_reg.h	92;"	d
PLL1_OCSEL	C6748_gel_reg.h	43;"	d
PLL1_OCSEL	C6748_gel_reg.h	78;"	d
PLL1_OSCDIV1	C6748_gel_reg.h	50;"	d
PLL1_OSCDIV1	C6748_gel_reg.h	85;"	d
PLL1_PID	C6748_gel_reg.h	40;"	d
PLL1_PID	C6748_gel_reg.h	75;"	d
PLL1_PLLCMD	C6748_gel_reg.h	54;"	d
PLL1_PLLCMD	C6748_gel_reg.h	89;"	d
PLL1_PLLCTL	C6748_gel_reg.h	42;"	d
PLL1_PLLCTL	C6748_gel_reg.h	77;"	d
PLL1_PLLDIV1	C6748_gel_reg.h	47;"	d
PLL1_PLLDIV1	C6748_gel_reg.h	82;"	d
PLL1_PLLDIV10	C6748_gel_reg.h	102;"	d
PLL1_PLLDIV10	C6748_gel_reg.h	67;"	d
PLL1_PLLDIV11	C6748_gel_reg.h	103;"	d
PLL1_PLLDIV11	C6748_gel_reg.h	68;"	d
PLL1_PLLDIV12	C6748_gel_reg.h	104;"	d
PLL1_PLLDIV12	C6748_gel_reg.h	69;"	d
PLL1_PLLDIV13	C6748_gel_reg.h	105;"	d
PLL1_PLLDIV13	C6748_gel_reg.h	70;"	d
PLL1_PLLDIV14	C6748_gel_reg.h	106;"	d
PLL1_PLLDIV14	C6748_gel_reg.h	71;"	d
PLL1_PLLDIV15	C6748_gel_reg.h	107;"	d
PLL1_PLLDIV15	C6748_gel_reg.h	72;"	d
PLL1_PLLDIV16	C6748_gel_reg.h	108;"	d
PLL1_PLLDIV16	C6748_gel_reg.h	73;"	d
PLL1_PLLDIV2	C6748_gel_reg.h	48;"	d
PLL1_PLLDIV2	C6748_gel_reg.h	83;"	d
PLL1_PLLDIV3	C6748_gel_reg.h	49;"	d
PLL1_PLLDIV3	C6748_gel_reg.h	84;"	d
PLL1_PLLDIV4	C6748_gel_reg.h	61;"	d
PLL1_PLLDIV4	C6748_gel_reg.h	96;"	d
PLL1_PLLDIV5	C6748_gel_reg.h	62;"	d
PLL1_PLLDIV5	C6748_gel_reg.h	97;"	d
PLL1_PLLDIV6	C6748_gel_reg.h	63;"	d
PLL1_PLLDIV6	C6748_gel_reg.h	98;"	d
PLL1_PLLDIV7	C6748_gel_reg.h	64;"	d
PLL1_PLLDIV7	C6748_gel_reg.h	99;"	d
PLL1_PLLDIV8	C6748_gel_reg.h	100;"	d
PLL1_PLLDIV8	C6748_gel_reg.h	65;"	d
PLL1_PLLDIV9	C6748_gel_reg.h	101;"	d
PLL1_PLLDIV9	C6748_gel_reg.h	66;"	d
PLL1_PLLM	C6748_gel_reg.h	45;"	d
PLL1_PLLM	C6748_gel_reg.h	80;"	d
PLL1_PLLSTAT	C6748_gel_reg.h	55;"	d
PLL1_PLLSTAT	C6748_gel_reg.h	90;"	d
PLL1_POSTDIV	C6748_gel_reg.h	51;"	d
PLL1_POSTDIV	C6748_gel_reg.h	86;"	d
PLL1_PREDIV	C6748_gel_reg.h	46;"	d
PLL1_PREDIV	C6748_gel_reg.h	81;"	d
PLL1_RSTYPE	C6748_gel_reg.h	41;"	d
PLL1_RSTYPE	C6748_gel_reg.h	76;"	d
PLL1_SECCTL	C6748_gel_reg.h	44;"	d
PLL1_SECCTL	C6748_gel_reg.h	79;"	d
PLL1_SYSTAT	C6748_gel_reg.h	60;"	d
PLL1_SYSTAT	C6748_gel_reg.h	95;"	d
PLL1_WAKEUP	C6748_gel_reg.h	53;"	d
PLL1_WAKEUP	C6748_gel_reg.h	88;"	d
PLLEN_MUX_SWITCH	C6748_gel_reg.h	269;"	d
PLL_LOCK_TIME_CNT	C6748_gel_reg.h	270;"	d
PLL_RESET_TIME_CNT	C6748_gel_reg.h	272;"	d
PLL_STABILIZATION_TIME	C6748_gel_reg.h	271;"	d
PSC0_BASE	C6748_gel_reg.h	111;"	d
PSC0_LPSC_SyncReset	C6748_gel.c	/^void PSC0_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {$/;"	f
PSC0_LPSC_enable	C6748_gel.c	/^void PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {$/;"	f
PSC0_LPSC_enableCore	C6748_gel.c	/^void PSC0_LPSC_enableCore(unsigned int PD, unsigned int LPSC_num) {$/;"	f
PSC0_MDCTL	C6748_gel_reg.h	114;"	d
PSC0_MDSTAT	C6748_gel_reg.h	115;"	d
PSC0_PTCMD	C6748_gel_reg.h	116;"	d
PSC0_PTSTAT	C6748_gel_reg.h	117;"	d
PSC1_BASE	C6748_gel_reg.h	112;"	d
PSC1_LPSC_SyncReset	C6748_gel.c	/^void PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num) {$/;"	f
PSC1_LPSC_enable	C6748_gel.c	/^void PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num) {$/;"	f
PSC1_LPSC_force	C6748_gel.c	/^void PSC1_LPSC_force(unsigned int LPSC_num) {$/;"	f
PSC1_MDCTL	C6748_gel_reg.h	119;"	d
PSC1_MDSTAT	C6748_gel_reg.h	120;"	d
PSC1_PTCMD	C6748_gel_reg.h	121;"	d
PSC1_PTSTAT	C6748_gel_reg.h	122;"	d
PSC_All_On	C6748_gel.c	/^void PSC_All_On() {$/;"	f
PSC_TIMEOUT	C6748_gel_reg.h	124;"	d
RX_DMA_INT_ENABLE	board.h	72;"	d
SAMPLING_RATE	board.h	50;"	d
SIZE_PARAMSET	board.h	80;"	d
SLOT_SIZE	board.h	46;"	d
SYS_BASE	C6748_gel_reg.h	239;"	d
TX_DMA_INT_ENABLE	board.h	71;"	d
VTPIO_CTL	C6748_gel_reg.h	176;"	d
VTP_TIMEOUT	C6748_gel_reg.h	197;"	d
WORD_SIZE	board.h	48;"	d
_AIC31_H_	aic31.h	41;"	d
_CODECIF_H_	codecif.h	40;"	d
board_init	board.c	/^void board_init(){$/;"	f
dataIdx	codecif.c	/^volatile unsigned int dataIdx = 0;$/;"	v
device_PLL0	C6748_gel.c	/^void device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {$/;"	f
device_PLL1	C6748_gel.c	/^void device_PLL1(unsigned int PLLM,unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3 ) {$/;"	f
gel_PLL_DDR_init	board.c	/^void  gel_PLL_DDR_init(void){$/;"	f
global_interrupt_init	board.c	/^void global_interrupt_init(){$/;"	f
init_tx_dma_buf	board.c	/^void init_tx_dma_buf(){$/;"	f
main	main.c	/^void main(){$/;"	f
rxBuf0	board.c	/^unsigned char rxBuf0[AUDIO_BUF_SIZE] = {0};$/;"	v
rxBuf1	board.c	/^unsigned char rxBuf1[AUDIO_BUF_SIZE] = {0};$/;"	v
rxBufPtr	board.c	/^static unsigned int const rxBufPtr[NUM_BUF] =$/;"	v	file:
rxDefaultPar	board.c	/^static struct EDMA3CCPaRAMEntry const rxDefaultPar =$/;"	v	file:
rx_dma_cnt	board.c	/^unsigned int rx_dma_cnt = 0;$/;"	v
rx_full	board.c	/^static volatile unsigned int rx_full = 0;$/;"	v	file:
savedBase	codecif.c	/^unsigned int savedBase;$/;"	v
slaveData	codecif.c	/^volatile unsigned int slaveData[3];$/;"	v
txBuf0	board.c	/^unsigned char txBuf0[AUDIO_BUF_SIZE] = {0};$/;"	v
txBuf1	board.c	/^unsigned char txBuf1[AUDIO_BUF_SIZE] = {0};$/;"	v
txBufPtr	board.c	/^static unsigned int const txBufPtr[NUM_BUF] =$/;"	v	file:
txCompFlag	codecif.c	/^volatile unsigned int txCompFlag = 1;$/;"	v
txDefaultPar	board.c	/^static struct EDMA3CCPaRAMEntry const txDefaultPar = $/;"	v	file:
txDefaultPar_old	board.c	/^static struct EDMA3CCPaRAMEntry const txDefaultPar_old = $/;"	v	file:
tx_buf_to_cpu_wr	board.c	/^static volatile unsigned int tx_buf_to_cpu_wr = 0;$/;"	v	file:
tx_dma_cnt	board.c	/^unsigned int tx_dma_cnt = 0;$/;"	v
tx_done	board.c	/^static volatile unsigned int tx_done = 0;$/;"	v	file:
