// *************************************************************************** //
// file     : HBFdmem2bk.v
// desp     : data memeory 2 bank 
// author   : duweitao@cuc.edu.cn
// date     : July.23th.2007
// version  : 0.1
// modified : 
// *************************************************************************** // 
`ifdef INCTSC
`include "timescale.v"
`endif
// module dchannel(), data channel 
module dmem2bk(
  CLK   ,   // clock , posedge 
  DWA0  ,   // data0 write address 
  DWA1  ,   // data1 write address 
  DWE0  ,   // data0 write enable
  DWE1  ,   // data1 write enable
  DWD0  ,   // data0 write data
  DWD1  ,   // data1 write data
  DRA0  ,   // data0 read address
  DRA1  ,   // data1 read address
  DRD0  ,   // data read data 0 
  DRD1  );  // data read data 1 



// global param
parameter DATAWL    = 0;    //  data word length
parameter ADDRWL    = 0;    //  address word length
parameter C2Q       = 0;    // clock to Q time in ns

input CLK, DWE0, DWE1; 
input [ADDRWL-1:0]  DWA0, DWA1, DRA0, DRA1;
input [DATAWL-1:0]  DWD0, DWD1; 
output [DATAWL-1:0] DRD0, DRD1;

dpram U_bank0(
  .WE      (DWE0    ),   // write enable
  .WCLK    (CLK     ),   // write clock
  .RCLK    (CLK     ),   // read clock   
  .WA      (DWA0    ),   // write address
  .RA      (DRA0    ),   // read address
  .WD      (DWD0    ),   // write data
  .RD      (DRD0    ));  // read data
defparam U_bank0.DATAWL    = DATAWL;
defparam U_bank0.ADDRWL    = ADDRWL;
defparam U_bank0.C2Q       = C2Q   ;

dpram U_bank1(
  .WE      (DWE1    ),   // write enable
  .WCLK    (CLK     ),   // write clock
  .RCLK    (CLK     ),   // read clock   
  .WA      (DWA1    ),   // write address
  .RA      (DRA1    ),   // read address
  .WD      (DWD1    ),   // write data
  .RD      (DRD1    ));  // read data
defparam U_bank1.DATAWL    = DATAWL;
defparam U_bank1.ADDRWL    = ADDRWL;
defparam U_bank1.C2Q       = C2Q   ;

endmodule   // module dchannel()
///////////////////////////////////////////////////////////////////////////////////////
module dpram(
  WE      ,   // write enable
  WCLK    ,   // write clock
  RCLK    ,   // read clock   
  WA      ,   // write address
  RA      ,   // read address
  WD      ,   // write data
  RD      );  // read data
// external set param
parameter DATAWL    = 0;
parameter ADDRWL    = 0;
parameter C2Q       = 0;
  input                    WE, WCLK, RCLK;
  input   [ADDRWL -1:0]    WA, RA; 
  input   [DATAWL -1:0]    WD;
  output  [DATAWL -1:0]    RD;

  reg[DATAWL-1:0] RD;
  reg[DATAWL-1:0] mem [(1<<ADDRWL)-1:0];

  always @ (posedge WCLK) begin
    if(WE)
      mem[WA] <= #C2Q WD;
  end
  always @ (posedge RCLK) begin
    RD  <= #C2Q mem[RA];
  end
// ######################################  
// synopsys translate_off                  
// ######################################  

  // task DumpDpRAM, get the content of RAM[addr]
  task DumpDpRAM; 
  input     [ADDRWL-1  :0] addr    ;
  output    [DATAWL-1 :0]  content ;
  begin
    content = mem[addr];
  end       // task begin
  endtask   // task DumpDpRAM

  // task RAMInit, initialize the RAM content
  task RAMInit;
    integer i;
    reg[DATAWL-1:0] initData;
  begin
    initData = 'hAAAA;
    // initData = (1<<DATAWL) - 1;
    for( i = 0; i < (1<<ADDRWL); i = i + 1)
      mem[i] = initData;
  end
  endtask
  initial begin
    RAMInit();
    $display("module dpram().RAMInit()called @ %0d", $time);
  end
// ###################################### 
// synopsys translate_on                  
// ###################################### 
//
endmodule   // module dptbram() 

///////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////
