library verilog;
use verilog.vl_types.all;
entity crdctl is
    generic(
        COEFWL          : integer := 0;
        K1              : integer := 0;
        K2              : integer := 0;
        C2Q             : integer := 0;
        PCYMAX          : integer := 0;
        PCYWL           : integer := 0;
        PCYIDL          : integer := 0;
        CADDRWL         : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DINEN           : in     vl_logic;
        PECY            : in     vl_logic_vector;
        CRD             : in     vl_logic_vector;
        RE              : out    vl_logic;
        CRA             : out    vl_logic_vector;
        COEF            : out    vl_logic_vector
    );
end crdctl;
