library verilog;
use verilog.vl_types.all;
entity dchnnel is
    generic(
        INPUTWL         : integer := 0;
        OUTPUTWL        : integer := 0;
        COEFWL          : integer := 0;
        K1              : integer := 0;
        K2              : integer := 0;
        K1LOG2          : integer := 0;
        K2LOG2          : integer := 0;
        C2Q             : integer := 0;
        PCYWL           : integer := 0;
        OCYWL           : integer := 0;
        PCYMAX          : integer := 0;
        PCYIDL          : integer := 0;
        ADDRWL          : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DINEN           : in     vl_logic;
        DIN             : in     vl_logic_vector;
        PECY            : in     vl_logic_vector;
        COEF            : in     vl_logic_vector;
        DOUT            : out    vl_logic_vector;
        DOUTEN          : out    vl_logic;
        OUTIDX          : out    vl_logic_vector(1 downto 0);
        CLKOUT          : out    vl_logic
    );
end dchnnel;
