library verilog;
use verilog.vl_types.all;
entity stim is
    generic(
        INPUTWL         : integer := 0;
        OUTPUTWL        : integer := 0;
        STIMLEN         : integer := 0;
        num_cycle_in    : integer := 0;
        time_SETUP      : integer := 0;
        period_CLK      : integer := 0
    );
    port(
        CLK             : out    vl_logic;
        RST             : out    vl_logic;
        DINI            : out    vl_logic_vector;
        DINQ            : out    vl_logic_vector;
        DINEN           : out    vl_logic
    );
end stim;
