library verilog;
use verilog.vl_types.all;
entity HBF2L is
    generic(
        INPUTWL         : integer := 16;
        OUTPUTWL        : integer := 16;
        COEFWL          : integer := 16;
        K1              : integer := 16;
        K1LOG2          : integer := 4;
        K2              : integer := 8;
        K2LOG2          : integer := 3;
        C2Q             : integer := 2;
        PCYWL           : integer := 6;
        PCYMAX          : integer := 31;
        CADDRWL         : integer := 5;
        DADDRWL         : integer := 5;
        OCYWL           : integer := 6
    );
    port(
        RST             : in     vl_logic;
        CLK             : in     vl_logic;
        DINEN           : in     vl_logic;
        DINI            : in     vl_logic_vector;
        DINQ            : in     vl_logic_vector;
        DOUTEN          : out    vl_logic;
        DOUTI           : out    vl_logic_vector;
        DOUTQ           : out    vl_logic_vector;
        OUTIDX          : out    vl_logic_vector(1 downto 0);
        CLKOUT          : out    vl_logic
    );
end HBF2L;
