library verilog;
use verilog.vl_types.all;
entity pe is
    generic(
        C2Q             : integer := 0;
        DATAWL          : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        SUMCLR          : in     vl_logic;
        DATA0           : in     vl_logic_vector;
        DATA1           : in     vl_logic_vector;
        COEF            : in     vl_logic_vector;
        PEEN            : in     vl_logic;
        PEOUT           : out    vl_logic_vector;
        PEOE            : out    vl_logic
    );
end pe;
