library verilog;
use verilog.vl_types.all;
entity harness_filter is
    generic(
        STIMLEN         : integer := 512;
        INPUTWL         : integer := 16;
        OUTPUTWL        : integer := 16;
        COEFWL          : integer := 16;
        num_cycle_in    : integer := 0;
        time_SETUP      : integer := 0;
        period_CLK      : integer := 0
    );
end harness_filter;
