module mac(
 RST    ,   // reset, high
 CLK    ,   // clock
 X1     ,   // input data1
 X2     ,   // input data2
 C      ,   // coef
 OUT    );  // output data

parameter IWIDTH = 18;
parameter OWIDTH = 36;

input                           RST, CLK;
input   signed [IWIDTH-1:0]     X1, X2, C;
output  signed [IWIDTH-1:0]     OUT;

reg signed    [IWIDTH-1:0]    x1R1, x2R1, cR1;

reg signed    [OWIDTH-1:0]    OUT;

reg signed    [IWIDTH  :0]    add;
reg signed    [IWIDTH-1:0]    product;
reg signed    [OWIDTH-1:0]    addMultSum;

always @ (posedge CLK or posedge RST) begin
  if (RST) begin
    x1R1 <= 0;
    x2R1 <= 0;
    cR1  <= 0;
    OUT  <= 0;
  end
  else begin
    x1R1 <= X1;
    x2R1 <= X2;
    cR1  <= C;
    OUT  <= addMultSum;
  end
end

always @ (x1R1 or x2R1 or cR1 or OUT or product or add) begin
  add        = x1R1 + x2R1;
  product    = add * cR1;
  addMultSum = product + OUT;
end


endmodule
