library verilog;
use verilog.vl_types.all;
entity outbuf is
    generic(
        DATAWL          : integer := 0;
        C2Q             : integer := 0;
        PCYWL           : integer := 0;
        K1              : integer := 0;
        K2              : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        XNBK01          : in     vl_logic;
        DATA0           : in     vl_logic_vector;
        DATA1           : in     vl_logic_vector;
        PEOUT           : in     vl_logic_vector;
        PEOE            : in     vl_logic;
        PECY            : in     vl_logic_vector;
        DOUT            : out    vl_logic_vector;
        DOUTEN          : out    vl_logic;
        OUTIDX          : out    vl_logic_vector(1 downto 0);
        CLKOUT          : out    vl_logic
    );
end outbuf;
