library verilog;
use verilog.vl_types.all;
entity compareOut is
    generic(
        OUTPUTWL        : integer := 0;
        STIMLEN         : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DOUT            : in     vl_logic_vector;
        DOUTEN          : in     vl_logic;
        OUTIDX          : in     vl_logic_vector(1 downto 0)
    );
end compareOut;
