library verilog;
use verilog.vl_types.all;
entity testcase1 is
    generic(
        period_CLK      : integer := 10;
        time_SETUP      : integer := 8;
        time_RESET      : integer := 0;
        num_period_RESET: integer := 4;
        num_cycle_in    : integer := 32
    );
end testcase1;
