library verilog;
use verilog.vl_types.all;
entity dpram is
    generic(
        DATAWL          : integer := 0;
        ADDRWL          : integer := 0;
        C2Q             : integer := 0
    );
    port(
        WE              : in     vl_logic;
        WCLK            : in     vl_logic;
        RCLK            : in     vl_logic;
        WA              : in     vl_logic_vector;
        RA              : in     vl_logic_vector;
        WD              : in     vl_logic_vector;
        RD              : out    vl_logic_vector
    );
end dpram;
