library verilog;
use verilog.vl_types.all;
entity dwrctl is
    generic(
        C2Q             : integer := 0;
        ADDRWL          : integer := 0;
        DATAWL          : integer := 0;
        K1              : integer := 0;
        K1LOG2          : integer := 0;
        K2              : integer := 0;
        K2LOG2          : integer := 0;
        WRY1PCY         : integer := 0;
        PCYWL           : integer := 0;
        PCYMAX          : integer := 0;
        PCYIDL          : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DINEN           : in     vl_logic;
        DIN             : in     vl_logic_vector;
        PECY            : in     vl_logic_vector;
        PEOUT           : in     vl_logic_vector;
        X1POS           : out    vl_logic_vector;
        Y1POS           : out    vl_logic_vector;
        WA0             : out    vl_logic_vector;
        WA1             : out    vl_logic_vector;
        WE0             : out    vl_logic;
        WE1             : out    vl_logic;
        WD0             : out    vl_logic_vector;
        WD1             : out    vl_logic_vector
    );
end dwrctl;
