library verilog;
use verilog.vl_types.all;
entity dmem2bk is
    generic(
        DATAWL          : integer := 0;
        ADDRWL          : integer := 0;
        C2Q             : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        DWA0            : in     vl_logic_vector;
        DWA1            : in     vl_logic_vector;
        DWE0            : in     vl_logic;
        DWE1            : in     vl_logic;
        DWD0            : in     vl_logic_vector;
        DWD1            : in     vl_logic_vector;
        DRA0            : in     vl_logic_vector;
        DRA1            : in     vl_logic_vector;
        DRD0            : out    vl_logic_vector;
        DRD1            : out    vl_logic_vector
    );
end dmem2bk;
