library verilog;
use verilog.vl_types.all;
entity dumprtl is
    generic(
        INPUTWL         : integer := 0;
        OUTPUTWL        : integer := 0;
        COEFWL          : integer := 0;
        K1              : integer := 0;
        K1LOG2          : integer := 0;
        K2              : integer := 0;
        K2LOG2          : integer := 0;
        C2Q             : integer := 0;
        D_ADDRWL        : integer := 0;
        PCYWL           : integer := 0
    );
end dumprtl;
