library verilog;
use verilog.vl_types.all;
entity drdctl is
    generic(
        C2Q             : integer := 0;
        PCYIDL          : integer := 0;
        PCYMAX          : integer := 0;
        PCYWL           : integer := 0;
        K1              : integer := 0;
        K1LOG2          : integer := 0;
        K2              : integer := 0;
        K2LOG2          : integer := 0;
        DATAWL          : integer := 0;
        ADDRWL          : integer := 0;
        WRY1PCY         : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DIN             : in     vl_logic_vector;
        DINEN           : in     vl_logic;
        PECY            : in     vl_logic_vector;
        DRD0            : in     vl_logic_vector;
        DRD1            : in     vl_logic_vector;
        X1POS           : in     vl_logic_vector;
        Y1POS           : in     vl_logic_vector;
        SUMCLR          : out    vl_logic;
        PEEN            : out    vl_logic;
        DRA0            : out    vl_logic_vector;
        DRA1            : out    vl_logic_vector;
        DRE0            : out    vl_logic;
        DRE1            : out    vl_logic;
        XNBK01          : out    vl_logic;
        DATA0           : out    vl_logic_vector;
        DATA1           : out    vl_logic_vector
    );
end drdctl;
