library verilog;
use verilog.vl_types.all;
entity pecnt is
    generic(
        C2Q             : integer := 0;
        PCYMAX          : integer := 0;
        PCYWL           : integer := 0;
        PCYIDL          : integer := 0
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DINEN           : in     vl_logic;
        PECY            : out    vl_logic_vector
    );
end pecnt;
