# Reading D:/Modeltech_6.0/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "E:/IPbeach/hbFIR/current/HDL/syn/simulation/modelsim/timing_tb.mpf" 
# Loading project timing_tb
vsim work.testcase1
# vsim work.testcase1 
# Loading work.testcase1
# Loading work.harness_filter
# Loading work.stim
# Loading work.HBF2L
# Loading work.cycloneii_ram_block
# Loading work.cycloneii_ram_register
# Loading work.cycloneii_ram_pulse_generator
# Loading work.cycloneii_lcell_comb
# Loading work.cycloneii_lcell_ff
# Loading work.cycloneii_mac_out
# Loading work.cycloneii_io
# Loading work.cycloneii_mux21
# Loading work.cycloneii_dffe
# Loading work.cycloneii_asynch_io
# Loading work.cycloneii_clkctrl
# Loading work.cycloneii_mux41
# Loading work.cycloneii_ena_reg
# Loading work.cycloneii_mac_mult
# Loading work.cycloneii_mac_data_reg
# Loading work.cycloneii_mac_sign_reg
# Loading work.cycloneii_mac_mult_internal
# Loading work.compareOut
# Loading work.CYCLONEII_PRIM_DFFE
# Loading HBF2L_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /testcase1  File: E:/IPbeach/hbFIR/current/HDL/syn/simulation/modelsim/HBF2L_tb.v
add wave sim:/testcase1/U_hflt/U_hbf/RST
add wave sim:/testcase1/U_hflt/U_hbf/CLK
add wave sim:/testcase1/U_hflt/U_hbf/DINEN
add wave sim:/testcase1/U_hflt/U_hbf/DINI
add wave sim:/testcase1/U_hflt/U_hbf/DINQ
add wave sim:/testcase1/U_hflt/U_hbf/DOUTEN
add wave sim:/testcase1/U_hflt/U_hbf/DOUTI
add wave sim:/testcase1/U_hflt/U_hbf/DOUTQ
add wave sim:/testcase1/U_hflt/U_hbf/OUTIDX
add wave sim:/testcase1/U_hflt/U_hbf/CLKOUT
run -all
# compareOut: open out dump file @0, fidOutDump =           2
# stim.CodeRamInit() Called @ 0
# compareOut.CodeRamInit() Called @ 0
# stim.Reset() called @ time 100, reset DUT 4 clock period
# testcase1 run at time 321
# 
# testcase1 off at time 230129
# 
# -------------------------------------------------------------------------
# TOTAL RTL MISMATCH RESULTS IS          0
# --------------------------------------------------------------------------
# Break at E:/IPbeach/hbFIR/current/HDL/syn/simulation/modelsim/HBF2L_tb.v line 65
